Advanced ternary CAM circuits on 0.13μm logic process technology

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2004, Pages 465-468

  Roth, Alan ^a,b   Foss, Dick ^a   McKenzie, Robert ^a   Perry, Douglas ^a,c  

^a MOSAID Technologies Inc   (Canada)

^b Alereon Inc   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

CAM cell; CAM redundancy; CMOS; Macro; Ternary CAM

Indexed keywords

CAM CELL; CAM REDUNDANCY; MACRO; POWER CONSUMPTION;

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED MANUFACTURING; EMBEDDED SYSTEMS; LOGIC GATES; MICROPROCESSOR CHIPS; REDUNDANCY; TRANSISTORS;

LOGIC CIRCUITS;

EID: 17044404649     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. H. Noda, K. Inoue, H. Mattausch, T. Koide, K. Arimoto. "A cost-efficient Dynamic Ternary CAM in 130 nm CMOS Technology with Planar Complementary Capacitors and TSR Architecture". 2003 Symposium on VLSI Circuits Digest of Technical Papers.
2. G. Kasai, Y. Takarabe, K. Furumi, M. Yoneda. "200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits Ternary CAM with New Charge Injection Match Detect Circuits and Bank Selection Scheme". 2003 Custom Integrated Circuits Digest of Technical Papers.
3. C.A. Zukowski, S.Y. Wang, "Use of Selective Precharge for Low Power on the Match Lines of Content Addressable Memories", Workshop on Memory Technology, Design and Testing, August 11-12 1997, p. 64-68.
4. H. Higuchi, S. Tachibana, M. Minami, T. Nagano, "A 5mW, 10ns Cycle TLB Using a High Performance CAM with Low Power Match Detection Circuits", IEICE Transactions on Electron Devices, vol. E79-C, no. 6, June 1996, p. 757-762.