메뉴 건너뛰기




Volumn 2, Issue , 2002, Pages 319-324

Design for low-power, low-cost, and high-reliability precomputation-based content-addressable memory

Author keywords

Associative memory; CADCAM; Circuit synthesis; CMOS process; Computer aided manufacturing; Energy consumption; MOS devices; Reliability; Very large scale integration; Voltage

Indexed keywords

ASSOCIATIVE PROCESSING; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED MANUFACTURING; DESIGN; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; MEMORY ARCHITECTURE; MOS DEVICES; RELIABILITY; VLSI CIRCUITS;

EID: 79959267812     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2002.1115248     Document Type: Conference Paper
Times cited : (10)

References (9)
  • 2
    • 0025505981 scopus 로고
    • A 1.2-million transistor 33-MHz 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM
    • Oct.
    • M. Motomura, J. Toyoura, K. Hirata, H. Ooka, H. Yamada, and T. Enomoto, "A 1.2-million transistor 33-MHz 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM," IEEE J. Solid-State Circuits, vol. 25, pp. 1158-1165, Oct. 1990.
    • (1990) IEEE J. Solid-State Circuits , vol.25 , pp. 1158-1165
    • Motomura, M.1    Toyoura, J.2    Hirata, K.3    Ooka, H.4    Yamada, H.5    Enomoto, T.6
  • 4
    • 0030362868 scopus 로고    scopus 로고
    • A new protocol processing architecture for high-speed networks
    • Nov.
    • T. Matsuda and K. Matsuda, "A new protocol processing architecture for high-speed networks," in Proc. IEEE GLOBECOM, Nov. 1996, pp. 798-803.
    • (1996) Proc. IEEE GLOBECOM , pp. 798-803
    • Matsuda, T.1    Matsuda, K.2
  • 5
    • 0035369412 scopus 로고    scopus 로고
    • A design for high-speed low-power CMOS fully parallel content-addressable memory macros
    • June
    • H. Miyatake, M. Tanaka, and Y. Mori, "A design for high-speed low-power CMOS fully parallel content-addressable memory macros," IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 956-968, June 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.6 , pp. 956-968
    • Miyatake, H.1    Tanaka, M.2    Mori, Y.3
  • 6
    • 0024718690 scopus 로고
    • A ternary content-addressable search engine
    • Aug.
    • J. P. Wade and C. G. Sodini, "A ternary content-addressable search engine," IEEE J. Solid-State Circuits, vol. 24, pp. 1003-1013, Aug. 1989.
    • (1989) IEEE J. Solid-State Circuits , vol.24 , pp. 1003-1013
    • Wade, J.P.1    Sodini, C.G.2
  • 7
    • 0035307453 scopus 로고    scopus 로고
    • A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell
    • Apr.
    • P. F. Lin and J. B. Kuo, "A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 666-675, Apr. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.4 , pp. 666-675
    • Lin, P.F.1    Kuo, J.B.2
  • 9
    • 0030285287 scopus 로고    scopus 로고
    • A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies
    • Nov.
    • T. Miw, H. Yamada, Y. Hirota, T. Satoh, and H. Hara, "A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies", IEEE J. Solid-State Circuit, vol. 31, no. 11, pp. 1601-1609, Nov., 1996.
    • (1996) IEEE J. Solid-State Circuit , vol.31 , Issue.11 , pp. 1601-1609
    • Miw, T.1    Yamada, H.2    Hirota, Y.3    Satoh, T.4    Hara, H.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.