A CAM With Mixed Serial-Parallel Comparison for Use in Low Energy Caches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 3, 2004, Pages 325-329

  Efthymiou, Aristides ^a   Garside, Jim D ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

Asynchronous design; Content addressable memory; Low power design

Indexed keywords

AMPLIFIERS (ELECTRONIC); COMPUTER AIDED DESIGN; ENERGY UTILIZATION; MOS DEVICES; PARALLEL PROCESSING SYSTEMS; RANDOM ACCESS STORAGE; SIGNAL THEORY; TRANSISTORS;

ASYNCHRONOUS DESIGN; CONTENT-ADDRESSABLE MEMORY; LEAST SIGNIFICANT BITS (LSB); LOW-POWER DESIGN;

CACHE MEMORY;

EID: 2142656433     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.824298     Document Type: Conference Paper

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