Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 383-386

  Pagiamtzis, Kostas ^a   Sheikholeslami, Ali ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; LOGIC GATES; MOSFET DEVICES; TRANSCEIVERS;

GLOBAL SEARCH LINE; HIERARCHICAL SEARCH LINE ARCHITECTURE; PIPELINES MATCH LINE ARCHITECTURE; VERTICAL SEARCH LINE;

ASSOCIATIVE STORAGE;

EID: 0242611950     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. T.-B. Pei and C. Zukowski, "Putting routing tables in silicon," IEEE Network Magazine, vol. 6, no. 1, pp. 42-50 January 1992.
2. L. Chisvin and R. J. Duckworth, "Content-addressable and associative memory: Alternatives to the ubiquitous RAM," IEEE Computer, vol. 22, no. 7, pp. 51-64, July 1989.
3. H. Miyatake, M. Tanaka, and Y. Mori, "A design for high-speed low-power CMOS fully parallel content-addressable memory macros," IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 956-968, June 2001.
4. I. Arsovski, T. Chandler and A. Sheikholeslami, "A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme," IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 155-158, January 2003.
5. I. Arsovski and A. Sheikholeslami, "A current-saving match-line sensing scheme for content-addressable memories," in IEEE International Solid-State Circuits Conference Technical Digest, 2003, pp. 304-305, 494.
6. C.A. Zukowski and S.-Y. Wang, "Use of selective precharge for low-power content-addressable memories," in Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 3, 1997, pp. 1788-1791.
7. F. Shafai, K. J. Schultz, G. F. R. Gibson, A. G. Bluschke, and D. E. Somppi, "Fully parallel 30-MHz, 2.5-Mb CAM," IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1690-1696, November 1998.
8. H. Zhang, V. George, and J.M. Rabaey, "Low-swing on-chip signaling techniques: Effectiveness and robustness," IEEE Trans. VLSI Syst., vol. 8, no. 3, pp. 264-272, June 2000.
9. NanoSim Reference Guide, Synopsys, March 2002.