Fully parallel integrated CAM/RAM using preclassification to enable large capacities

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 5, 1996, Pages 689-699

  Schultz, Kenneth J ^a,b,c,d,e,f   Gulak, P Glenn ^a,b,g,h,i,j  

^a IEEE

^b UNIVERSITY OF TORONTO   (Canada)

^c NORTEL NETWORKS   (Canada)

^d UNIVERSITY OF MANITOBA   (Canada)

^e University of Toronto ^*

^f Université Laval

^g Stanford University

^h TELECOM PARISTECH   (France)

ⁱ ISSCC Sign Proc Tech Subcommittee

^j Program Secretary for ISSCC

more..

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; ELECTRIC DELAY LINES; MONOLITHIC INTEGRATED CIRCUITS; PHASE LOCKED LOOPS; TIMING CIRCUITS;

DELAY LINE LOOPS; MONOLITHIC DIGITAL CLOCK GENERATOR; ON CHIP CLOCKING; RING COUNTER;

ASSOCIATIVE STORAGE;

EID: 0030146233     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.509851     Document Type: Article

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