-
1
-
-
0001499971
-
SOI for digital CMOS VLSI: Design considerations and advances
-
April
-
C. T. Chuang et al. "SOI for digital CMOS VLSI: design considerations and advances," Proc. IEEE, vol. 86, no. 4, April 1998.
-
(1998)
Proc. IEEE
, vol.86
, Issue.4
-
-
Chuang, C.T.1
-
2
-
-
0032638543
-
SOI digital CMOS VLSI - A design perspective
-
C. T. Chuang and R. Puri, "SOI digital CMOS VLSI - a design perspective," Design Automation Conf., 1999, pp. 709-714.
-
(1999)
Design Automation Conf.
, pp. 709-714
-
-
Chuang, C.T.1
Puri, R.2
-
5
-
-
0041589378
-
Analysis and Minimization Techniques for total Leakage Considering Gate Oxide Leakage
-
D. Lee, et al., "Analysis and Minimization Techniques for total Leakage Considering Gate Oxide Leakage," Design Automation Conf, 2003.
-
(2003)
Design Automation Conf
-
-
Lee, D.1
-
7
-
-
0036045608
-
Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs
-
K Rim, et al., "Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs," Symp. VLSI Technology, 2002, pp. 98-99.
-
(2002)
Symp. VLSI Technology
, pp. 98-99
-
-
Rim, K.1
-
9
-
-
0033697180
-
Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors
-
T. Ghani, et al., "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," Symp. VLSI Technology, 2000, pp. 174-175.
-
(2000)
Symp. VLSI Technology
, pp. 174-175
-
-
Ghani, T.1
-
10
-
-
0033725602
-
Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling
-
W. C. Lee and C. Hu, "Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling," Symp. VLSI Technology, 2000, pp. 198-199.
-
(2000)
Symp. VLSI Technology
, pp. 198-199
-
-
Lee, W.C.1
Hu, C.2
-
12
-
-
0012088265
-
Effect of gate-to-body tunneling current on PD/SOI CMOS circuits
-
Tokyo, Japan
-
C. T. Chuang, R. Puri, and K. Bernstein, "Effect of gate-to-body tunneling current on PD/SOI CMOS circuits," Int'I Conf. on Solid State Devices and Materials, Tokyo, Japan, 2001, pp. 262-263.
-
(2001)
Int'I Conf. on Solid State Devices and Materials
, pp. 262-263
-
-
Chuang, C.T.1
Puri, R.2
Bernstein, K.3
-
13
-
-
0036458721
-
Effects of gate-to-body tunneling current on pass-transistor based PD/ SOI CMOS circuits
-
C. T. Chuang and R. Puri, "Effects of gate-to-body tunneling current on pass-transistor based PD/SOI CMOS circuits," Proc. IEEE Int'l SOI Conf., 2002, pp. 121-122.
-
(2002)
Proc. IEEE Int'l SOI Conf.
, pp. 121-122
-
-
Chuang, C.T.1
Puri, R.2
-
15
-
-
0034795708
-
Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM
-
R. V. Joshi, et al., "Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM," Symp. VLSI Technology, 2001, pp. 75-76.
-
(2001)
Symp. VLSI Technology
, pp. 75-76
-
-
Joshi, R.V.1
-
16
-
-
0036454483
-
Tendency of full depletion due to gate tunneling current
-
H. Wan, et al., "Tendency of full depletion due to gate tunneling current," Proc. IEEE Int'l SOI Conf., 2002, pp. 140-141.
-
(2002)
Proc. IEEE Int'l SOI Conf.
, pp. 140-141
-
-
Wan, H.1
-
18
-
-
0036456289
-
Thermal conductivity model for thin silicon-on-insulator layers at high temperatures
-
M. Ashegi, et al., "Thermal conductivity model for thin silicon-on-insulator layers at high temperatures," Proc. IEEE Int'l SOI Conf., 2002, pp. 51-52.
-
(2002)
Proc. IEEE Int'l SOI Conf.
, pp. 51-52
-
-
Ashegi, M.1
-
19
-
-
84945713471
-
Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement
-
February
-
C. Hu, et al., "Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement", IEEE Transactions on Electron Devices, Vol. ED32, No. 2, pp-375-382, February, 1985
-
(1985)
IEEE Transactions on Electron Devices
, vol.ED32
, Issue.2
, pp. 375-382
-
-
Hu, C.1
-
20
-
-
0034230311
-
Time dependent breakdown of ultrathin gate oxide
-
Jul
-
A.M. Yassine, et al., "Time dependent breakdown of ultrathin gate oxide", Electron Devices, IEEE Transactions on, Volume: 47 Issue: 7, Jul 2000, Page(s): 1416-1420
-
(2000)
Electron Devices, IEEE Transactions on
, vol.47
, Issue.7
, pp. 1416-1420
-
-
Yassine, A.M.1
-
22
-
-
0036081925
-
Impact of negative bias temperature instability on digital circuit reliability
-
40th Annual, 2002
-
V. Reddy, et al., "Impact of negative bias temperature instability on digital circuit reliability", Reliability Physics Symposium Proceedings, 2002. 40th Annual, 2002, Page(s): 248-254
-
(2002)
Reliability Physics Symposium Proceedings
, pp. 248-254
-
-
Reddy, V.1
-
23
-
-
0031210445
-
Floating body effects in partially-depleted SOI CMOS circuits
-
August
-
P. F. Lu, et al., "Floating body effects in partially-depleted SOI CMOS circuits," IEEE J. Solid-State Circuits, vol. 32, no. 8, August 1997, pp. 1241-1253.
-
(1997)
IEEE J. Solid-state Circuits
, vol.32
, Issue.8
, pp. 1241-1253
-
-
Lu, P.F.1
-
24
-
-
0030658640
-
Dual-mode parasitic bipolar effect in dynamic CVSL XOR circuit with floating-body partially-depleted SOI devices
-
Taipei, Taiwan
-
C. T. Chuang, et al., "Dual-mode parasitic bipolar effect in dynamic CVSL XOR circuit with floating-body partially-depleted SOI devices," Proc. Tech. Papers, Int'l Symp. on VLSI Tech., Syst., and Applications, Taipei, Taiwan, 1997, pp. 288-292.
-
(1997)
Proc. Tech. Papers, Int'l Symp. on VLSI Tech., Syst., and Applications
, pp. 288-292
-
-
Chuang, C.T.1
-
27
-
-
0033338762
-
A dynamic body discharge technique for SOI circuit applications
-
J. B. Kuang, et al., "A dynamic body discharge technique for SOI circuit applications," Proc. IEEE Int'l SOI Conf., 1999, pp. 77-78.
-
(1999)
Proc. IEEE Int'l SOI Conf.
, pp. 77-78
-
-
Kuang, J.B.1
-
28
-
-
0035309061
-
Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology
-
April
-
J. B. Kuang, D. H. Allen, and C. T. Chuang, "Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology," IEEE J. Solid-State Circuits, vol. 36, no. 4, April 2001, pp. 597-604.
-
(2001)
IEEE J. Solid-state Circuits
, vol.36
, Issue.4
, pp. 597-604
-
-
Kuang, J.B.1
Allen, D.H.2
Chuang, C.T.3
-
29
-
-
0035158885
-
A tri-state body charge modulated SOI sense amplifier
-
J. B. Kuang and C. T. Chuang, "A tri-state body charge modulated SOI sense amplifier," Proc. IEEE Int'l SOI Conf., 2001, pp. 135-136.
-
(2001)
Proc. IEEE Int'l SOI Conf.
, pp. 135-136
-
-
Kuang, J.B.1
Chuang, C.T.2
-
30
-
-
0030216887
-
Minimizing floating-body-induced threshold voltage variation in partially depleted SOI CMOS
-
Aug.
-
A. Wei, et al., "Minimizing floating-body-induced threshold voltage variation in partially depleted SOI CMOS," IEEE Elec. Dev. letters, vol. 17, no. 8, Aug. 1996, pp. 391-394.
-
(1996)
IEEE Elec. Dev. Letters
, vol.17
, Issue.8
, pp. 391-394
-
-
Wei, A.1
-
32
-
-
0032306393
-
A guide to simulation of hysteretic gate delays based on physical understanding
-
T. W. Houston and S. Unnikrishnan, "A guide to simulation of hysteretic gate delays based on physical understanding," Proc. IEEE Int'l SOI Conf., 1998, pp. 121-122.
-
(1998)
Proc. IEEE Int'l SOI Conf.
, pp. 121-122
-
-
Houston, T.W.1
Unnikrishnan, S.2
-
33
-
-
0032599138
-
Hysteresis in floating-body PD/SOI CMOS circuits
-
Taipei, Taiwan
-
M. M. Pelella, et al., "Hysteresis in floating-body PD/SOI CMOS circuits," Symp. on VLSI Tech., Syst., and Applications, Taipei, Taiwan, 1999, pp. 278-281.
-
(1999)
Symp. on VLSI Tech., Syst., and Applications
, pp. 278-281
-
-
Pelella, M.M.1
-
34
-
-
0032319666
-
Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits
-
R. Puri and C. T. Chuang, "Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits," Proc. IEEE Int'l SOI Conf., 1998, pp. 103-104.
-
(1998)
Proc. IEEE Int'l SOI Conf.
, pp. 103-104
-
-
Puri, R.1
Chuang, C.T.2
-
36
-
-
0035167285
-
Measurement of history effect in PD/SOI single-ended CPL circuit
-
K. A. Jenkins, R. Puri, C. T. Chuang, and F. L. Pesavento, "Measurement of history effect in PD/SOI single-ended CPL circuit," Proc. IEEE Int'l SOI Conf., 2001, pp. 57-58.
-
(2001)
Proc. IEEE Int'l SOI Conf.
, pp. 57-58
-
-
Jenkins, K.A.1
Puri, R.2
Chuang, C.T.3
Pesavento, F.L.4
-
37
-
-
0033324758
-
Detailed analysis of the gate delay variability in partially depleted SOI CMOS circuits
-
I. Aller and K. E. Kroell, "Detailed analysis of the gate delay variability in partially depleted SOI CMOS circuits," Proc. IEEE Int'l SOI Conf., 1999, pp. 40-41.
-
(1999)
Proc. IEEE Int'l SOI Conf.
, pp. 40-41
-
-
Aller, I.1
Kroell, K.E.2
-
38
-
-
0035159829
-
Self-heating enhanced impact ionization in SOI MOSFETs
-
P. Su, et al., "Self-heating enhanced impact ionization in SOI MOSFETs," Proc. IEEE Int'l SOI Conf., 2001, pp. 31-32.
-
(2001)
Proc. IEEE Int'l SOI Conf.
, pp. 31-32
-
-
Su, P.1
-
39
-
-
0036458326
-
An impact ionization model for SOI circuit simulation
-
P. Su, et al., "An impact ionization model for SOI circuit simulation," Proc. IEEE Int'l SOI Conf., 2002, pp. 201-202.
-
(2002)
Proc. IEEE Int'l SOI Conf.
, pp. 201-202
-
-
Su, P.1
-
42
-
-
0034785110
-
Carrier mobility enhancement in strained Sion-insulator fabricated by wafer bonding
-
L. J. Huang, et al., "Carrier mobility enhancement in strained Sion-insulator fabricated by wafer bonding," Symp. VLSI Technology, 2001, pp. 57-58.
-
(2001)
Symp. VLSI Technology
, pp. 57-58
-
-
Huang, L.J.1
-
43
-
-
0036456607
-
Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS device/circuit
-
K. Kim, et al., "Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS device/circuit," Proc. IEEE Int'l SOI Conf., 2002, pp. 17-19.
-
(2002)
Proc. IEEE Int'l SOI Conf.
, pp. 17-19
-
-
Kim, K.1
-
44
-
-
0031232922
-
Will physical scalability sabotage performance gains?
-
Sep
-
D. Matzke, "Will physical scalability sabotage performance gains?", Computer, Volume: 30 Issue: 9, Sep 1997, Page(s): 37-39
-
(1997)
Computer
, vol.30
, Issue.9
, pp. 37-39
-
-
Matzke, D.1
-
46
-
-
0034202654
-
Computing with Molecules
-
June
-
M. Reed, et al., "Computing with Molecules", Scientific American, June, 2000.
-
(2000)
Scientific American
-
-
Reed, M.1
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