Will physical scalability sabotage performance gains?

Computer

Volumn 30, Issue 9, 1997, Pages 37-39

  Matzke, Doug ^a,b,c,d  

^a TEXAS INSTRUMENTS   (United States)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

^c UNIVERSITY OF TEXAS   (United States)

^d IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; TRANSISTORS;

ONCHIP DEVICES;

MICROPROCESSOR CHIPS;

EID: 0031232922     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.612245     Document Type: Article

References (5)

1. M. Bohr, "Interconnect Scaling - The Real Limiter to High Performance ULSI," Proc. Int'l Electron Devices Meeting, IEEE Press, New York, 1995, pp. 241-244.
2. D. Hillis, "New Computer Architectures and Their Relationship to Physics or Why Computer Science is No Good," Int'l J. Theoretical Physics, Vol. 21, Nos. 3, 4, 1982, pp. 255-262.
3. C. Lemonds, "A 500 MHz, One Volt, 16 by 16 Multiplier for DSP Cores," Proc. VLSI Signal Processing Workshop, IEEE Press, New York, 1996, pp. 481-484.
4. F. Preparata, "Horizons of Parallel Computation," Tech. Report CS-93-20, Brown University, Providence, R.I.
5. W. Dally, "A Universal Parallel Computer Architecture," New Generation Computing, Vol. 11, 1993, pp. 227-249.