Variable-length input huffman coding for system-on-a-chip test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 6, 2003, Pages 783-796

  Gonciari, Paul T ^a   Al Hashimi, Bashir M ^a   Nicolici, Nicola ^b  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^b MCMASTER UNIVERSITY   (Canada)

Author keywords

Automated test equipment (ATE); Embedded core testing; System on a chip (SOC); Test data compression; Test resource partitioning; Test set encoding; Test time reduction

Indexed keywords

DATA REDUCTION; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; SIGNAL ENCODING;

HUFFMAN CODING;

ELECTRONIC EQUIPMENT TESTING;

EID: 0038718528     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.811451     Document Type: Conference Paper

References (41)

1. A. Jas, J. Ghosh-Dastidar, and N. A. Touba, "Scan vector compression/decompression using statistical coding," in Proc. IEEE VLSI Test Symp., Apr. 1999, pp. 114-121.
2. A. Chandra and K. Chakrabarty, "System-on-a-chip test data compression and decompression architectures based on Golomb codes," IEEE Trans. Computer-Aided Design, vol. 20, pp. 113-120, Mar. 2001.
3. _, "Frequency-Directed Run-Length (FDR) codes with application to system-on-a-chip test data compression," in Proc. IEEE VLSI Test Symp., Apr. 2001, pp. 114-121.
4. J. Marinissen, Y. Zorian, R. Kapur, T. Taylor, and L. Whetsel, "Toward a standard for embedded core test: an example," in Proc. IEEE Int. Test Conf., Sept. 1999, pp. 616-627.
5. G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, and J. Rajski, "Logic BIST for large industrial designs: real issues and case studies," in Proc. IEEE Int. Test Conf., Sept. 1999, pp. 358-367.
6. Y. Zorian, S. Dey, and M. Rodgers, "Test of future system-on-chips," in Proc. Int. Conf. Computer-Aided Design, Nov. 2000, pp. 392-398.
7. J. Rajski, "DFT for high-quality low cost manufacturing test," in Proc. Asian Test Symp., Nov. 2001, pp. 3-8.
8. I. Hamzaoglu and J. H. Patel, "Test set compaction algorithms for combinational circuits," in Proc. Int. Conf. Computer-Aided Design, Nov. 1998, pp. 283-289.
9. I. Pomeranz, L. Reddy, and S. Reddy, "COMPACTEST: a method to generate compact test set for combinational circuits," IEEE Trans. Computer-Aided Design, vol. 12, pp. 1040-1049, July 1993.
10. T. Yamaguchi, M. Tilgner, M. Ishida, and D. S. Ha, "An efficient method for compressing test data to reduce the test data download time," in Proc. IEEE Int. Test Conf., 1997, pp. 79-88.
11. M. Ishida, D. S. Ha, and T. Yamaguchi, "Compact: a hybrid method for compressing lets data," in Proc. IEEE VLSI Test Symp., Apr. 1998, pp. 62-69.
12. B. Koenemann, "LFSR-coded test patterns for scan designs," in Proc. IEEE Eur. Test Conf., Mar. 1991, pp. 237-242.
13. H.-J. Wunderlich and G. Kiefer, "Bit-flipping BIST," in Proc. Int. Conf. Computer-Aided Design., Nov. 1996.
14. N. A. Touba and E. J. McCluskey, "Altering a pseudorandom bit sequence for scan-based BIST," in Proc. IEEE Int. Test Conf., Oct. 1996, pp. 167-175.
15. G. Kiefer and H.-J. Wunderlich, "Deterministic BIST with multiple scan chains," in Proc. IEEE Int. Test Conf., Oct. 1998, pp. 1057-1064.
16. J. Rajski, J. Tyszer, and N. Zacharia, "Test data decompression for multiple scan designs with boundary scan," IEEE Trans. Comput., vol. 47, pp. 1188-1200, Nov. 1998.
17. G. Kiefer, H. Vranken, E. J. Marinissen, and H.-J. Wunderlich, "Application of deterministic logic bist on industrial circuits," in Proc. IEEE Int. Test Conf., Oct. 2000, pp. 105-114.
18. M. L. Bushnell and V. D. Agrawal, Esentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Norwell, MA: Kluwer, 2000.
19. J.-F. Li, R.-S. Tzeng, and C.-W. Wu, "Diagnostic data compression techniques for embedded memories with built-in self-test," J. Electron. Testing: Theory Applicat., vol. 18, no. 4, pp. 515-527, 2002.
20. J. T. Chen, J. Rajski, J. Khare, O. Kebichi, and W. Maly, "Enabling embedded memory diagnosis via test response compression," in Proc. IEEE VLSI Test Symp., May 2001, pp. 292-298.
21. D. Das and N. A. Touba, "Reducing test data volume using external/LBIST hybrid test patterns," in Proc. IEEE Int. Test Conf., Oct. 2000, pp. 115-122.
22. C. Krishna, A. Jas, and N. A. Touba, "Test vector encoding using partial LFSR reseeding," in Proc. IEEE Int. Test Conf., Oct. 2001, pp. 885-893.
23. A. Jas, C. Krishna, and N. A. Touba, "Hybrid BIST based on weighted pseudo-random testing: a new test resource partitioning scheme," in Proc. IEEE VLSI Test Symp., May 2001, pp. 2-8.
24. D. Kay and S. Mourad, "Compression technique for interactive BIST application," in Proc. IEEE VLSI Test Symp., May 2001, pp. 9-14.
25. D. Kay, S. Chung, and S. Mourad, "Embedded test control schemes for compression in SOCs," in Proc. ACM/IEEE Design Automation Conf., June 2002, pp. 679-684.
26. R. Dorsch and H.-J. Wunderlich, "Tailoring ATPG for embedded testing," in Proc. IEEE Int. Test Conf., Oct. 2001, pp. 530-537.
27. I. Bayraktaroglu and A. Orailoglu, "Test volume and application time reduction through scan chain concealment," in Proc. ACM/IEEE Design Automation Conf., vol. 38, June 2001, pp. 151-155.
28. B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, and D. Wheater, "A SmartBIST variant with guaranteed encoding," in Proc. Asian Test Symp., Nov. 2001, pp. 325-330.
29. V. Iyengar, K. Chakrabarty, and B. Murray, "Deterministic built-in pattern generation for sequential circuits," J. Electron. Testing: Theory Applicat., vol. 15, no. 1, pp. 97-114, 1999.
30. A. Jas and N. Touba, "Test vector decompression via cyclical scan chains and its application to testing core-based designs," in Proc. IEEE Int. Test Conf., Oct. 1998, pp. 458-464.
31. _, "Using an embedded processor for efficient deterministic testing of systems-on-a-chip," in Proc. Int. Conf. Computer Design, Oct. 1999, pp. 418-423.
32. A. El-Maleh, S. al Zahir, and E. Khan, "A geometric-primitives-based compression scheme for testing systems-on-chip," in Proc. IEEE VLSI Test Symp., Apr. 2001, pp. 114-121.
33. S. Reda and A. Orailoglu, "Reducing test application time through test data mutation encoding," in Proc. Design, Automation, Test Eur., Mar. 2002, pp. 387-393.
34. T. Cover and J. Thomas, Elements of Information Theory. New York: Wiley, 1991.
35. V. D. Agrawal and T. J. Chakraborty, "High-performance circuit testing with slow-speed testers," in Proc. IEEE Int. Test Conf., Apr. 1995, pp. 302-310.
36. D. Heidel, S. Dhong, P. Hofstee, M. Immediato, K. Nowka, J. Silberman, and K. Stawiasz, "High-speed serialiazing/deserializing design-for-test methods for evaluating a 1 GHz microprocessor," in Proc. IEEE VLSI Test Symp., Apr. 1998, pp. 234-238.
37. H. Ichihara, A. Ogava, T. Inoue, and A. Tamura, "Dynamic test compression using statistical coding," in Proc. Asian Test Symp., Nov. 2001, pp. 143-148.
38. H. Ichihara, K. Kinoshita, I. Pomeranz, and S. Reddy, "Test transformation to improve compaction by statistical encoding," in Proc. Int. Conf. VLSI Design, Jan. 2000, pp. 294-299.
39. IGATE, Univ. Illinois., Urbana-Champaign. [Online] Available: www.crhc.uiuc.edu/IGATE
40. F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," in Proc. Int. Symp. Circuits Syst., May 1989, pp. 1929-1934.
41. Synopsys Inc., Design Compiler Reference Manual, 2002.