Compression technique for interactive BIST application

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 9-14

  Kay, D ^a   Mourad, S ^a  

^a SANTA CLARA UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CORRELATION METHODS; DATA COMPRESSION; EMBEDDED SYSTEMS; ENCODING (SYMBOLS); FAILURE ANALYSIS; PROBABILITY;

CIRCUIT UNDER TEST; FAULT COVERAGE; RANDOM PATTERN RESISTANT FAULTS; TEST RESOURCES PARTITION;

INTEGRATED CIRCUIT TESTING;

EID: 0034985101     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (32)

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