Deterministic built-in pattern generation for sequential circuits

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 15, Issue 1, 1999, Pages 97-114

  Iyengar, Vikram ^a   Chakrabarty, Krishnendu ^b,d,e   Murray, Brian T ^c  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b Duke University   (United States)

^c DELPHI CORPORATION   (United States)

^d INDIAN INSTITUTE OF TECHNOLOGY   (India)

^e UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; ENCODING (SYMBOLS); FLIP FLOP CIRCUITS; SEMICONDUCTOR DEVICE MODELS; SEQUENTIAL CIRCUITS; STATISTICAL METHODS;

COMMA CODING; DETERMINISTIC BUILT-IN PATTERN GENERATION; EMBEDDED CORE TESTING; HUFFMAN CODING;

SEMICONDUCTOR DEVICE TESTING;

EID: 0033322164     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008384201996     Document Type: Article

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