A SmartBIST variant with guaranteed encoding

Proceedings of the Asian Test Symposium

Volumn , Issue , 2001, Pages 325-330

  Koenemann, Bernd ^a   Barnhart, Carl ^a   Keller, Brion ^a   Snethen, Tom ^a   Farnsworth, Owen ^a   Wheater, Donald ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DATA COMPRESSION; DECODING; ENCODING (SYMBOLS); REAL TIME SYSTEMS; VECTORS;

AUTOMATIC TEST EQUIPMENT; AUTOMATIC TEST PATTERN GENERATION; SCAN TEST VECTORS;

INTEGRATED CIRCUIT TESTING;

EID: 0035704290     PISSN: 10817735     EISSN: None     Source Type: Journal    
DOI: 10.1109/ATS.2001.990304     Document Type: Article

References (14)

1. LFS-coded test patterns for scan designs
2. Logic DFT and Test e-source partitioning for 100M gate asverbal ICs
3. OPMISR: Accelerated scan with on-product signatures
4. OPMISR: The foundation fo compressed ATPG vectors
5. Logic BIST for large industrial designs: Real issues and case studies
6. On the use of linear sums in exhaustive testing
7. Test volume and application time reduction through scan chain concealment
8. Reducing test application time for full scan embedded cores
9. Controllable LFSR fo BIST
10. Extending SelfTest: Sing clock-gates for LFS-based test pattern encoding