Enabling embedded memory diagnosis via test response compression

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 292-298

  Chen, J T ^a   Rajski, J ^a   Khare, J ^a   Kebichi, O ^a   Maly, W ^a  

^a NONE

Author keywords

BIST; Bitmap; Diagnosis; Memory repair; Process monitoring; RAM testing

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; COMPUTER SIMULATION; DYNAMIC RANDOM ACCESS STORAGE; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; STATIC RANDOM ACCESS STORAGE;

EMBEDDED MEMORY; MEMORY REPAIR; PROCESS MONITORING; TEST RESPONSE COMPRESSION;

BUILT-IN SELF TEST;

EID: 0035017465     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Process monitoring oriented testing
2. Failure analysis of high-density CMOS SRAMs using realistic defect modeling and Iddq testing
3. DFT advances in motorola's MPC7400, a PowerPC microprocessor
4. Semiconductor manufacturing process monitoring using built-in self-test for embedded memories
5. SRAM-based extraction of defect characteristics
6. A method and apparatus for diagnosing memory using self-testing circuits