Hard ware-optimal test register insertion

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 6, 1998, Pages 531-539

  Strode, Albrecht P ^a,b   Wunderlich, Hans Joachim ^a,b  

^a UNIVERSITY OF KARLSRUHE   (Germany)

^b UNIVERSITY OF STUTTGART   (Germany)

Author keywords

BILBO; Built in self test; CBILBO; Test register insertion

Indexed keywords

ALGORITHMS; COST EFFECTIVENESS; DESIGN; FLOWCHARTING; OPTIMIZATION; TESTING;

TEST REGISTERS;

LOGIC CIRCUITS;

EID: 0032090792     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.703833     Document Type: Article

References (40)

1. K.-T. Cheng and V. D. Agrawal A partial scan method for sequential circuits with feedback IEEE Trans. Comput. vol. 39 pp. 544-547 Apr. 1990.
2. V. Chickermane and J. H. Patel An optimization based approach to the partial scan problem in Proc. Int. Test Conf. 1990 pp. 377-386.
3. R. Gupta R. Gupta and M. A. Breuer The BALLAST methodology for structured partial scan design IEEE Trans. Comput. vol. 39 pp. 538-544 Apr. 1990.
4. A. Kunzmann and H.-J. Wunderlich An analytical approach to the partial scan problem J. Electronic Testing: Theory and Applications vol. 1 no. 2 pp. 163-174 1990.
5. D. H. Lee and S. M. Reddy On determining scan flip-flops in partialscan designs in Proc. Int. Conf. CAD 1990 pp. 322-325.
6. M. R. Garey and D. S. Johnson Computers and intractability. Ne York: Freeman 1979.
7. S. T. Chakradhar A. Balakrishnan and V. D. Agrawal An exact algorithm for determining partial scan flip-flops in Proc. ACM/IEEE Design Automation Conf. San Diego CA 1994 pp. 81-86.
8. B. Koenemann J. Mucha and G. Zwiehoff Built-in logic block observation techniques in Proc. Test Conf. Cherry Hill NJ 1979 pp. 37-41.
9. H.-J. Wunderlich Self test using unequiprobable random patterns in Proc. Int. Symp. Fault-Tolerant Computing 1987 pp. 258-263.
10. M. S. Abadir and M. A. Breuer A knowledge-based system for designing testable VLSI chips IEEE Design & Test Mag. vol. 2 no. 3 pp. 56-68 1985.
11. A. Krasniewski and A. Albicki Automatic design of exhaustively selftesting chips with BILBO modules in Proc. Int. Test Conf. 1985 pp. 362-371.
12. C. A. Papachristou S. Chiu and H. Harmanani A data path synthesis method for self-testable designs in Proc. ACM/IEEE Design Automation Conf. 1991 pp. 378-384.
13. S.-P. Lin C. A. Njinda and M. A. Breuer A systematic approach for designing testable VLSI circuits in Proc. Int. Conf. CAD 1991 pp. 496-499.
14. A. Krasniewski and S. Pilarski Circular self-test Path: A low cost BIST technique for VLSI circuits IEEE Trans. Computer-Aided Design vol. 8 pp. 46-55 Jan. 1989.
15. F. Corno P. Prinetto and M. Sonza Reorda Making the circular selftest path effective for real circuits in Proc. Int. Test Conf. 1994 pp. 949-957.
16. G. L. Craig C. R. Kime and K. K. Saluja Test scheduling and control for VLSI built-in self-test IEEE Trans. Comput. vol. 37 pp. 1099-1109 Sept. 1988.
17. A. P. Stroele Partitioning and hierarchical description of self-testable designs IFIP Transactions A: Computer Science and Technology vol. A-42 pp. 113-122 1994.
18. O. F. Haberl and H.-J. Wunderlich The synthesis of self-test control logic in Proc. COMPEURO 1989 pp. 5.134-5.136.
19. C. L. Hudson and G. D. Peterson Parallel self-test with pseudo-random test patterns in Proc. Int. Test Conf. 1987 pp. 954-963.
20. R. Illman and S. Clarke Built-in self-test of the MACROLAN chip in Proc. Int. Test Conf. 1989 pp. 735-744.
21. S. Das Gupta R. G. Walther E. B. Eichelberger and T. W. Williams An enhancement to LSSD and some applications of LSSD in reliability availability and serviceability in Proc. Int. Symp. Fault-Tolerant Computing 1981 pp. 32-34.
22. M. J. Ohletz T. W. Williams and J. P. Mucha Overhead in scan and self-test designs in Proc. Int. Test Conf. 1987 pp. 460-4170.
23. L.-T. Wang and E. J. McCluskey Concurrent built-in logic block observer (CBILBO) in Proc. Int. Symp. Circuits and Systems 1986 pp. 1054-1057.
24. V. D. Agrawal C. R. Kime and K. K. Saluja A tutorial on built-in self-test Part 1: Principles IEEE Design & Test Mag. vol. 10 no. 1 pp. 73-82 1993.
25. A tutorial on built-in self-test Part 2: Applications IEEE Design & Test Mag. vol. 10 no. 2 pp. 69-77 1993.
26. L. Avra Allocation and assignment in high-level synthesis for selftestable data paths in Proc. Int. Test Conf. 1991 pp. 463-4172.
27. H. Harmanani and C. A. Papachristou An improved method for RTL synthesis with testability tradeoffs in Proc. Int. Conf. CAD 1993 pp. 30-35.
28. M. L. Flottes D. Hammad and B. Rouzeyre Automatic synthesis o BISTed data paths from high level specification in Proc. Europea Design and Test Conf.. 1994 pp. 591-598.
29. F. Brglez D. Bryan and K. Kozminski Combinational profiles o sequential benchmark circuits in Proc. Int. Symp. Circuits and Systems 1989 pp. 1929-1934.
30. D. Goldberg Computer arithmetic in Computer Architecture: Quantitative Approach J. L. Hennessy and D. A. Patterson Eds. Sa Mateo CA: Morgan Kaufmann 1990.
31. S. Narayanan C. Njinda and M. Breuer Optimal sequencing of sca registers in Proc. Int. Test Conf. 1992 pp. 293-302.
32. A. P. Stroele and H.-J. Wunderlich Configuring flip-flops to BIS registers in Proc. Int. Test Conf. 1994 pp. 939-948.
33. Y. Zorian A distributed BIST control scheme for complex VLS devices in Proc. VLSI Test Symp. 1993 pp. 4-9.
34. L. Avra and E. J. McCluskey Behavioral synthesis of testable system with VHDL in Proc. COMPCON Spring'90 1990 pp. 410-115.
35. A. Mujumdar R. Jain and K. Saluja Incorporating testability considerations in high-level synthesis J. Electronic Testing: Theory an Applications vol. 5 no. 1 pp. 43-55 1994.
36. A. Mujumdar R. Jain and K. Saluja Behavioral synthesis of testabl designs in Proc. Int. Symp. Fault-Tolerant Computing 1994 pp 436-145.
37. D. Kagaris and S. Tragoudas Partial scan with retiming in Proc ACM/IEEE Design Automation Conf. 1993 pp. 249-254.
38. S. T. Chakradhar and S. Dey Resynthesis and retiming for optimu partial scan in Proc. ACM/IEEE Design Automation Conf. 1994 pp 87-93.
39. P. Pan and C. L. Liu Partial scan with pre-selected scan signals i Proc. ACM/IEEE Design Automation Conf. 1995 pp. 189-194.
40. S. Dey M. Potkonjak and R. Roy Synthesizing designs with lowcardinality minimum feedback vertex set for partial scan application in Proc. VLSI Test Symp. 1994 pp. 2-7.