Circular Self-Test Path: A Low-Cost BIST Technique for VLSI Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 8, Issue 1, 1989, Pages 46-55

  Krasniewski, Andrzej ^a   Pilarski, Szawomir ^a  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, FLIP FLOP; INTEGRATED CIRCUIT TESTING--COMPUTER SIMULATION;

BUILT-IN SELF TEST (BIST); CIRCULAR SELF-TEST PATH; SELF-TEST VLSI CIRCUITS; TEST RESPONSE COMPACTION; VLSI TEST PATTERN GENERATION;

INTEGRATED CIRCUITS, VLSI;

EID: 0024480981     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.21818     Document Type: Article

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