Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1994, Pages 2-7

  Dey, Sujit ^a   Potkonjak, Miodrag ^a   Roy, Rabindra ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; FEEDBACK; FLIP FLOP CIRCUITS; LOGIC DESIGN; SEQUENTIAL CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION; CONTROL DATA FLOW GRAPH; FULL SCAN DESIGN;

ELECTRIC NETWORK SYNTHESIS;

EID: 0028744857     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)