Behavioral synthesis of testable designs

Digest of Papers - International Symposium on Fault-Tolerant Computing

Volumn , Issue , 1994, Pages 436-445

  Mujumdar, Ashutosh ^a   Jain, Rajiv ^a   Saluja, Kewal ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER NETWORKS; COMPUTER SYSTEMS; DIGITAL ARITHMETIC; ELECTRIC NETWORK SYNTHESIS; GRAPH THEORY; HEURISTIC METHODS; LOGIC DESIGN; OPTIMIZATION; SHIFT REGISTERS; STORAGE ALLOCATION (COMPUTER);

BEHAVIORAL SYNTHESIS; HIGH LEVEL SYNTHESIS TOOLS; REGISTER TRANSFER LEVEL; TESTABILITY CONSTRAINED BINDING USING NETWORK FLOWS; TESTABLE DESIGNS;

LOGIC CIRCUITS;

EID: 0028128772     PISSN: 07313071     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)