Optimal Seguencing of Scan Registers

Proceedings - International Test Conference

Volumn 1992-January, Issue , 1992, Pages 293-302

  Narayanan, S ^a   Njinda, C ^a   Breuer, M ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Circuit testing; Costs; Degradation; Design for testability; Flip flops; Hardware; Multiplexing; Pins; Registers; Test equipment

Indexed keywords

COMPUTER HARDWARE; COSTS; DEGRADATION; DESIGN FOR TESTABILITY; EQUIPMENT TESTING; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; MULTIPLEXING; MULTIPLEXING EQUIPMENT;

ALGORITHMIC TECHNIQUES; CIRCUIT TESTING; PINS; REGISTERS; SINGLE CHAINS; TEST APPLICATION TIME; TEST APPLICATIONS; TEST EQUIPMENTS;

CHAINS;

EID: 0003380966     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.1992.527836     Document Type: Conference Paper

References (0)