Resynthesis and retiming for optimum partial scan

Proceedings - Design Automation Conference

Volumn , Issue , 1994, Pages 87-93

  Chakradhar, Srimat T ^a   Dey, Sujit ^a  

^a NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT THEORY; COMPUTATIONAL COMPLEXITY; EQUIVALENT CIRCUITS; GRAPH THEORY; LOGIC GATES; SEQUENTIAL CIRCUITS; SHIFT REGISTERS;

MINIMUM FEEDBACK VERTEX SET; PARTIAL SCAN; RESYNTHESIS; RETIMING; SEQUENTIAL BENCHMARKS;

FLIP FLOP CIRCUITS;

EID: 0028552980     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/196244.196288     Document Type: Conference Paper

References (9)