The BALLAST Methodology for Structured Partial Scan Design

IEEE Transactions on Computers

Volumn 39, Issue 4, 1990, Pages 538-544

  Gupta, Rajesh ^a   Gupta, Rajiv ^a   Breuer, Melvin A ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Balanced sequential structures; design for testability; partial incomplete scan design; sequential circuit testing; single pattern testability; test pattern formatting

Indexed keywords

LOGIC CIRCUITS--AUTOMATIC TESTING;

AUTOMATIC TEST PATTERN GENERATION; BALLAST METHODOLOGY; IRREDUNDANT FAULTS; PARTIAL SCAN DESIGN; STRUCTURED DESIGN;

LOGIC CIRCUITS, SEQUENTIAL;

EID: 0025417241     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.54846     Document Type: Article

References (11)

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