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Volumn 39, Issue 4, 1990, Pages 544-548

A Partial Scan Method for Sequential Circuits with Feedback

Author keywords

Design for testability; scan design; sequential circuit testing; test generation

Indexed keywords

COMPUTER PROGRAMMING--ALGORITHMS; ELECTRONIC CIRCUITS, FLIP FLOP; LOGIC CIRCUITS--AUTOMATIC TESTING; MATHEMATICAL TECHNIQUES--GRAPH THEORY;

EID: 0025419945     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.54847     Document Type: Article
Times cited : (163)

References (12)
  • 1
    • 0019148843 scopus 로고
    • Incomplete scan path with an automatic test generation methodology
    • Nov.
    • E. Trischler, “Incomplete scan path with an automatic test generation methodology,” in Proc. Int. Test Conf., Nov. 1980, pp. 153–162.
    • (1980) Proc. Int. Test Conf. , pp. 153-162
    • Trischler, E.1
  • 5
    • 0024138663 scopus 로고
    • The BACK algorithm for sequential test generation
    • (ICCD-88), Rye Brook, NY, Oct.
    • W. T. Cheng, “The BACK algorithm for sequential test generation,” in Proc. Int. Conf. Comput. Design (ICCD-88), Rye Brook, NY, Oct. 1988, pp. 66–69.
    • (1988) Proc. Int. Conf. Comput. Design , pp. 66-69
    • Cheng, W.T.1
  • 6
    • 0024934584 scopus 로고
    • Testability analysis of synchronous sequential circuits based on structure data
    • Aug.
    • R. V. Hudli and S. C. Seth, “Testability analysis of synchronous sequential circuits based on structure data,” in Proc. Int. Test Conf., Aug. 1989, pp. 364–372.
    • (1989) Proc. Int. Test Conf. , pp. 364-372
    • Hudli, R.V.1    Seth, S.C.2
  • 9
    • 0024913805 scopus 로고
    • Combinational profile of sequential benchmark circuits
    • May
    • F. Brglez, D. Bryan, and K. Kozminski, “Combinational profile of sequential benchmark circuits,” in Proc. Int. Symp. Circuits Syst., May 1989, pp. 1929–1934.
    • (1989) Proc. Int. Symp. Circuits Syst. , pp. 1929-1934
    • Brglez, F.1    Bryan, D.2    Kozminski, K.3
  • 10
    • 0024946337 scopus 로고
    • Concurrent test generation and design for testability
    • May
    • K. T. Cheng and V. D. Agrawal, “Concurrent test generation and design for testability,” in Proc. Int. Symp. Circuits Syst., May 1989, pp. 1935–1938.
    • (1989) Proc. Int. Symp. Circuits Syst. , pp. 1935-1938
    • Cheng, K.T.1    Agrawal, V.D.2
  • 12
    • 0021407840 scopus 로고
    • A novel clocking technique for VLSI circuit testability
    • Apr.
    • M. R. Mercer and V. D. Agrawal, “A novel clocking technique for VLSI circuit testability,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 207–212, Apr. 1984.
    • (1984) IEEE J. Solid-State Circuits , vol.SC-19 , pp. 207-212
    • Mercer, M.R.1    Agrawal, V.D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.