Test Scheduling and Control for VLSI Built-In Self-Test

IEEE Transactions on Computers

Volumn 37, Issue 9, 1988, Pages 1099-1109

  Craig, Gary L ^a   Kime, Charles R ^b   Saluja, Kewal K ^b  

^a SYRACUSE UNIVERSITY   (United States)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

Built in self test; cliques; design for testability; graph coloring; scheduling; test control; VLSI circuit testing

Indexed keywords

INTEGRATED CIRCUIT TESTING -- COMPUTER AIDED ANALYSIS;

BUILT-IN-SELF-TEST (BIST); TEST SCHEDULING; VLSI BIST;

INTEGRATED CIRCUITS, VLSI;

EID: 0024070859     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.2260     Document Type: Article

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