메뉴 건너뛰기




Volumn 10, Issue 1, 1993, Pages 73-82

A Tutorial on Built-ln Self-Test Part 1: Principles

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; COMPUTER CIRCUITS; COSTS; DIGITAL CIRCUITS; INTEGRATED CIRCUIT TESTING;

EID: 0027556721     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.199807     Document Type: Article
Times cited : (186)

References (24)
  • 1
    • 0022044251 scopus 로고
    • Built-In Self-Test Techniques
    • Apr.
    • E.J. McCluskey, “Built-In Self-Test Techniques,” IEEE Design & Test of Computers, Vol. 2, No. 2, Apr. 1985, pp. 21–28.
    • (1985) IEEE Design & Test of Computers , vol.2 , Issue.2 , pp. 21-28
    • McCluskey, E.J.1
  • 2
    • 0022045890 scopus 로고
    • Built-In Self-Test Structures
    • Apr.
    • E.J. McCluskey, “Built-In Self-Test Structures,” IEEE Design & Test of Computers, Vol. 2, No. 2, Apr. 1985, pp. 29–36.
    • (1985) IEEE Design & Test of Computers , vol.2 , Issue.2 , pp. 29-36
    • McCluskey, E.J.1
  • 3
    • 0021411494 scopus 로고
    • Characterizing the LSI Yield Equation from Wafer Test Data
    • Apr.
    • S.C. Seth and V.D. Agrawal, “Characterizing the LSI Yield Equation from Wafer Test Data,” IEEE Trans. Computer-Aided Design, Vol. CAD-3, No. 4, Apr. 1984, pp. 123–126.
    • (1984) IEEE Trans. Computer-Aided Design , vol.CAD-3 , Issue.4 , pp. 123-126
    • Seth, S.C.1    Agrawal, V.D.2
  • 4
    • 0039671322 scopus 로고
    • In-Circuit Testing
    • Van Nostrand Reinhold, New York
    • I. Bateson, In-Circuit Testing, Van Nostrand Reinhold, New York, 1985.
    • (1985)
    • Bateson, I.1
  • 5
    • 0022909417 scopus 로고
    • Economically Viable Automatic Insertion of Self-Test Features for Custom VLSI
    • IEEE Computer Society Press, Los Alamitos, Calif., Sept.
    • A.P. Ambler et al., “Economically Viable Automatic Insertion of Self-Test Features for Custom VLSI,” Proc. Int’l Test Conf., IEEE Computer Society Press, Los Alamitos, Calif., Sept., 1986, pp. 232–243.
    • (1986) Proc. Int’l Test Conf. , pp. 232-243
    • Ambler, A.P.1
  • 6
    • 0026392981 scopus 로고
    • Economic Effects in Design and Test
    • Dec.
    • I.D. Dear, “Economic Effects in Design and Test” IEEE Design & Test of Computers, Vol. 8, No. 4, Dec. 1991, pp. 64–77.
    • (1991) IEEE Design & Test of Computers , vol.8 , Issue.4 , pp. 64-77
    • Dear, I.D.1
  • 7
    • 0021424216 scopus 로고
    • Self-Testing the Motorola MC6804P 2
    • May
    • J. Kuban and W. Bruce, “Self-Testing the Motorola MC6804P2,” IEEE Design & Test of Computers, Vol. 1, No. 2, May 1984, pp. 33–41.
    • (1984) IEEE Design & Test of Computers , vol.1 , Issue.2 , pp. 33-41
    • Kuban, J.1    Bruce, W.2
  • 8
    • 0025795335 scopus 로고
    • PEST: A Tool for Implementing Pseudo-Exhaustive Self-Test
    • Jan./Feb.
    • E. Wu, “PEST: A Tool for Implementing Pseudo-Exhaustive Self-Test,” AT&T Technical J., Vol. 70, No. 1, Jan./Feb. 1991, pp. 87–100.
    • (1991) AT&T Technical J. , vol.70 , Issue.1 , pp. 87-100
    • Wu, E.1
  • 12
    • 0025416171 scopus 로고
    • A Statistical Theory of Digital Circuit Testability
    • Apr.
    • S.C. Seth, V.D. Agrawal, and H. Farhat, “A Statistical Theory of Digital Circuit Testability,” IEEE Trans. Computers, Vol. C-39, No. 4, Apr. 1990, pp. 582–586.
    • (1990) IEEE Trans. Computers , vol.C-39 , Issue.4 , pp. 582-586
    • Seth, S.C.1    Agrawal, V.D.2    Farhat, H.3
  • 14
  • 15
    • 0002158127 scopus 로고
    • LFSR-Based Deterministic and Pseudorandom Test Pattern Generator Structures
    • IEEE CS Press
    • C. Dufaza and G. Cambon, “LFSR-Based Deterministic and Pseudorandom Test Pattern Generator Structures,” Proc. European Test Conf, IEEE CS Press, 1991, pp. 27–34.
    • (1991) Proc. European Test Conf , pp. 27-34
    • Dufaza, C.1    Cambon, G.2
  • 16
    • 0023533824 scopus 로고
    • Cellular Automata Used for Test Pattern Generation
    • IEEE CS Press
    • M. Khare and A. Albicki, “Cellular Automata Used for Test Pattern Generation,” Proc. Int’l Conf. Computer Design, IEEE CS Press, 1987, pp. 56–59.
    • (1987) Proc. Int’l Conf. Computer Design , pp. 56-59
    • Khare, M.1    Albicki, A.2
  • 17
    • 0025480910 scopus 로고
    • Cellular Automata-Based Self-Test for Programmable Data Paths
    • IEEE CS Press
    • J. van Sas, F. Catthoor, and H. De Man, “Cellular Automata-Based Self-Test for Programmable Data Paths,” Proc. Int’l Test Conf., IEEE CS Press, 1990, pp. 769–778.
    • (1990) Proc. Int’l Test Conf. , pp. 769-778
    • van Sas, J.1    Catthoor, F.2    De Man, H.3
  • 18
    • 0023846878 scopus 로고
    • Syndrome and Transition Count Are Uncorrelated
    • Jan.
    • N.R. Saxena and J.P. Robinson, “Syndrome and Transition Count Are Uncorrelated,” IEEE Trans. Information Theory, Vol. 34, Jan. 1988, pp. 64–69.
    • (1988) IEEE Trans. Information Theory , vol.34 , pp. 64-69
    • Saxena, N.R.1    Robinson, J.P.2
  • 19
    • 0024069136 scopus 로고
    • A Data Compression Technique for Built-In Self-Test
    • Sept. correction, Vol. C-38, No. 2, Feb. 1989, p. 320
    • S.M. Reddy, K.K. Saluja, and M.G. Karpovsky, “A Data Compression Technique for Built-In Self-Test,” IEEE Trans. Computers, Vol. C-37, No. 9, Sept. 1988, pp. 1151–1156; correction, Vol. C-38, No. 2, Feb. 1989, p. 320.
    • (1988) IEEE Trans. Computers , vol.C-37 , Issue.9 , pp. 1151-1156
    • Reddy, S.M.1    Saluja, K.K.2    Karpovsky, M.G.3
  • 20
    • 0025416278 scopus 로고
    • An Analysis of the Aliasing Probability of Multiple-Input Signature Registers in the Case of a 2m-ary Symmetric Channel
    • Apr.
    • K. Iwasaki and F. Arakawa, “An Analysis of the Aliasing Probability of Multiple-Input Signature Registers in the Case of a 2m-ary Symmetric Channel,” IEEE Trans. Computer-Aided Design, Vol. CAD-9, No. 4, Apr. 1990, pp. 427–438.
    • (1990) IEEE Trans. Computer-Aided Design , vol.CAD-9 , Issue.4 , pp. 427-438
    • Iwasaki, K.1    Arakawa, F.2
  • 21
    • 0025414787 scopus 로고
    • Aliasing Probability for Multiple-Input Signature Analyzer
    • Apr.
    • D.K. Pradhan, S.K. Gupta, and M.G. Karpovsky, “Aliasing Probability for Multiple-Input Signature Analyzer,” IEEE Trans. Computers, Vol. C-39, No. 4, Apr. 1990, pp. 586–591.
    • (1990) IEEE Trans. Computers , vol.C-39 , Issue.4 , pp. 586-591
    • Pradhan, D.K.1    Gupta, S.K.2    Karpovsky, M.G.3
  • 23
    • 0002237315 scopus 로고
    • Optimizing Error Masking in BIST by Output Data Modification
    • Feb.
    • Y. Zorian and V.K. Agarwal, “Optimizing Error Masking in BIST by Output Data Modification,” Electronic Testing: Theory and Applications, Vol. 1, Feb. 1990, pp. 59–72.
    • (1990) Electronic Testing: Theory and Applications , vol.1 , pp. 59-72
    • Zorian, Y.1    Agarwal, V.K.2
  • 24
    • 0026136645 scopus 로고
    • A Method of Reducing Aliasing in a Built-In Self-Test Environment
    • Apr.
    • K. Akiyama and K.K. Saluja, “A Method of Reducing Aliasing in a Built-In Self-Test Environment,” IEEE Trans. Computer-Aided Design, Vol. CAD-10, No. 4, Apr. 1991, pp. 548–553.
    • (1991) IEEE Trans. Computer-Aided Design , vol.CAD-10 , Issue.4 , pp. 548-553
    • Akiyama, K.1    Saluja, K.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.