Model and design of bipolar and MOS current-mode logic: CML, ECL and SCL digital circuits

Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits

Volumn , Issue , 2005, Pages 1-318

  Alioto, Massimo ^a   Palumbo, Gaetano ^b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84892218523     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/1-4020-2888-1     Document Type: Book

References (121)

1. [ACK93] D. Allstot, S. Chee, S. Kiaei, M. Shristawa, "Folded sourcecoupled logic vs. CMOS static logic for low-noise mixed-signal ICs, " IEEE Trans. on CAS - part I, vol. 40, no. 9, pp. 553-563, Sept. 1993.
2. [ADP02] M. Alioto, G. Di Cataldo, G. Palumbo, "Design of Low-Power High-Speed Bipolar Frequency Dividers", Electronics Letters, Vol. 38, No. 4, pp. 158-160, February 2002.
3. [ADR00] Auvergne, D., Daga, J.M., Rezzoug M. "Signal Transition Time Effect on CMOS Delay Evaluation, ", IEEE Trans. on Circuits and Systems - part I, vol. 47, no. 9, pp. 1362-1369, Sept. 2000.
4. [AM88] P. Antognetti, G. Massobrio, Semiconductor Device Modeling with Spice, McGraw-Hill, 1988.
5. [AMP03] M. Alioto, R. Mita, G. Palumbo, "Performance Evaluation of the Low-Voltage CML D-Latch Topology", Integration - The VLSI Journal, Vol. 36, No. 4, pp. 191-209, November 2003.
6. [AP99] M. Alioto, G. Palumbo, "Highly Accurate and Simple Models for CML and ECL Gates", IEEE Trans. on CAD, Vol. 18, No. 9, pp. 1369-1375, September 1999.
7. [AP991] M. Alioto, G. Palumbo, "CML and ECL: Optimized Design and Comparison", IEEE Trans. on CAS part I, Vol. 46, No. 11, pp. 1330-1341, November 1999.
8. [AP00] M. Alioto, G. Palumbo, "Modeling and Optimized Design of Current Mode MUX/XOR and D Flip-Flop", IEEE Trans. on CAS part II, Vol. 47, No. 5, pp. 452-461, May 2000.
9. [AP01] M. Alioto, G. Palumbo, "Oscillation Frequency in CML and ESCL Ring Oscillators", IEEE Trans. on CAS part I, Vol. 48, No. 2, pp. 210-214, February 2001.
10. [AP03] M. Alioto, G. Palumbo, "Design Strategies for Source Coupled Logic Gates, " IEEE Trans. on CAS - part I, Vol. 30, No. 4, pp.640-654, May 2003.
11. [AP031] M. Alioto, G. Palumbo, "Design of MUX, XOR and D-Latch SCL Gates", IEEE ISCAS 2003, Bangkok, pp. V261-V264, May 2003.
12. [APP02] M. Alioto - G. Palumbo - S. Pennisi, "Modeling of Source Coupled Logic Gates, " International Journal of Circuit Theory and Applications, Vol. 30, No. 4, pp.459-477, July, 2002.
13. [ARL95] L. Andersson, B. Rudberg, P. Lewin, M. Reed, S. Planer, S. Sundaram "Silicon Bipolar Chipset for SONET/SDH 10 Gb/s Fiber-Optic Communication Links, " IEEE Journal of Solid-State Circuits, vol. 30, no. 3, pp. 210-217, March 1995.
14. [BNK98] L. Bisdounis, S. Nikolaidis, O. Koufopavlou, "Analytical transient response of propagation delay evaluation of the CMOS inverter for short channel devices, " IEEE Jour. of Solid-State Circuits, vol. 33, no. 2, pp. 302-306, Feb. 1998.
15. [C92] C. Chuang, "Advanced Bipolar Circuits, " IEEE Circuits & Devices, pp. 32-36, November 1992.
16. [CBA88] E.-Chor, A. Brunnschweiler, P. Ashburn, "A Propagation-Delay Expression and its Application to the Optimization of Polysilicon Emitter ECL Processes, " IEEE Jour. of Solid-State Circ., Vol. 23, No. 1, pp. 251-259, February 1988.
17. [CB95a] A. Chandrakasan, R. Brodersen, "Minimizing Power Consumption in Digital CMOS Circuits, " Proc. of the IEEE, vol. 83, no. 4, pp. 498-523, 1995.
18. [CB95b] A. Chandrakasan, R. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publisher, 1995.
19. [CBF01] A. Chandrakasan, W. Bowhill, F. Fox, (Eds.), Design of High- Performance Microprocessor Circuits, IEEE Press 2001.
20. [CCK95] C. Choy, C. Chan, M. Ku, "A feedback control circuit design technique to suppress power noise in high speed output driver, " Proc. of ISCAS'95, pp. 307-310, April 1995.
21. [CCK97] C. Choy, C. Chan, M. Ku, J. Povazanec, "Design procedure of low-noise high-speed adaptive output drivers, " Proc. of ISCAS'97, pp. 1796-1799, 1997.
22. [CG73] B. Cochrun, A. Grabel, "A method for the Determination of the Transfer Function of electronic Circuits, " IEEE Trans. on Circuit Theory, Vol. CT-20, No. 1, pp. 16-20, Jan. 1973.
23. [CH99] Y. Cheng, C. Hu, MOSFET modeling & BSIM3 user's guide, Kluwer Academic Publishers, 1999.
24. [CHL92] C. Choy, C. Ho, G. Lunn, B. Lin, G. Fung "A BiCMOS Programmable Frequency Divider, " IEEE Trans. on Circuits and Systems part II, Vol. 39, No. 3, pp. 147-154, March 1992.
25. [CJ89] C. Choy, P. Jones, "Minimisation Tachnique for Series-Gated Emitter-Coupled Logic, " IEE Proc. Part G, vol. 136, no. 3, pp. 105-113, June 1989.
26. [CP86] K. Chu, D. Pulfrey, "Design Procedures for Differential Cascode Voltage Switch Circuits, " IEEE Jour. of Solid-state Circ., vol. SC- 21, no. 6, pp. 1082-1087, December 1986.
27. [CW98] H. Chang, J. Wu, "A 723-MHz 17.2-mW CMOS Programmable Counter, " IEEE Journal of Solid-State Circuits, vol. 33, no. 10, pp. 1572-1575, Oct. 1998.
28. [DKS90] B. Del Signore, D. Kerth, N. Sooch, E. Swanson, "A monolithic 20-b delta-sigma A/D converter, " IEEE Jour. Solid-State Circuits, vol. 25, pp. 1311-1317, Dec. 1990.
29. [DS03] B. De Muer, M. Steyaert, CMOS Fractional-N Synthesizers (Designfor High Spectral Purity and Monlithic Integration), Kluwer Academic Publishers, 2003.
30. [E48] W. Elmore, "The transient response of damped linear networks, " J. Appl. Phys., vol. 19, pp. 55-63, Jan. 1948.
31. [EBR94] S. Embabi, D. Brueske, K. Rachamreddy, "A BiCMOS low-power current mode gate, " IEEE Jour. of Solid-State Circuits, vol. 29, no. 6, pp. 741-745, June 1994.
32. [F90] W. Fang, "Accurate Analytical Delay Expressions for ECL and CML Circuits and Their Applications to Optimizing High-Speed Bipolar Circuits, " IEEE Jour. of Solid-State Circ., Vol. 25, No. 2, pp. 572-583, April 1990.
33. [F96] A. Felder, et al., "46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz Static Frequency Divider in Silicon Bipolar Technology, " IEEE Jour. Of Solid-State Circ., Vol. 31, No. 4, pp. 481-486, April 1996.
34. [F97] I. Fujimori et al., "A 5-V single chip delta-sigma audio A/D converter with 111 dB dynamic range, " IEEE Jour. of Solid-State Circuits, vol. 32, pp. 329-336, Mar. 1997.
35. [FMP96] A. Felder, M. Moller, J. Popp, J. Bock, H. Rein "46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz Static Frequency Divider in Silicon Bipolar Technology, " IEEE Jour. of Solid-State Circ., Vol. 31, No. 4, pp. 481-486, April 1996.
36. [FBA90] W. Fang, A. Brunnschweiler, P. Ashburn, "An Analytical Maximum Toggle Frequency Expression and its Application to Optimizing High-Speed ECL Frequency Dividers, " IEEE Jour. of Solid-State Circ., Vol. 25, No. 4, pp. 920-931, August 1990.
37. [GM93] P. Gray, R. Meyer, Analysis and Design of Analog Integrated Circuits (third edition), John Wiley & Sons, 1993.
38. [GMC91]H. Greub, J. McDonald, T. Creedon and T. Yamaguchi, "Highperformance standard cell library and modeling technique for differential advanced bipolar current tree logic, " IEEE Jour. of Solid-State Circuits, vol. 26, no. 5, pp. 749-762, May 1991.
39. [GMO90]M. Ghannam, R. Mertens, R. Van Overstraeten, ""An Analytical for the Determination of the Transient Response of CML and ECL Gates, " IEEE Trans. on Electron Devices, Vol. 37, No. 1, pp. 191- 201, January 1990.
40. [GT86] R. Gregorian, G. Temes, Analog MOS Integrated Circuits for signal processing, John Wiley & Sons, 1986.
41. [H95] Y. Harada, "Delay Components of a Current Mode Logic Circuit and Their Current Dependency, " IEEE Jour. of Solid-State Circ., Vol. 30, No. 1, pp. 54-60, January 1995.
42. [H96] J. Hauenschild, et al., "A Plastic Packaged 10 Gb/s BiCMOS Clock and Data Recovering 1:4-Demultiplexer with External VCO, " IEEE Jour. of Solid-State Circ., Vol. 31, No. 12, pp. 2056-2059, December 1996.
43. [H97] G. Hurkx, "The relevance of fT and fMAX for the Speed of a Bipolar CE Amplifier Stage, " IEEE Trans. on Electron Devices, Vol. 44, No. 5, pp. 775-781, May 1997.
44. [HFP01] C. Hung, B. Floyd, B. Park, K. O, "Fully Integrated 5.35-GHz CMOS VCOs and Prescalers, ", IEEE Trans. on Microwave Theory and Techniques vol. 49, no. 1, Jan. 2001.
45. [HLL99] A. Hajimiri, S. Limotyrakis, T. Lee, "Jitter and Phase Noise in Ring Oscillators, " IEEE Journal of Solid State Circuits, Vol. 34, No. 6, pp. 790-804, June 1999.
46. [HR99] F. Herzel, B. Razavi, "A Study of Oscillator Jitter Due to Supply and Substrate Noise, " IEEE Trans. on Circuits and Systems part II, Vol. 46, No. 1, pp. 56-62, January 1999.
47. [I95] N. Ishihara, et al., "3.5-Gb/s x 4-Ch Si Bipolar LSI's for Optical Interconnections, " IEEE Jour. of Solid-state Circ., Vol. 30, No. 12, pp. 1493-1500, December 1995.
48. [I951] K. Ishii, et al. "Very-High-Speed Si Bipolar Static Frequency Dividers with New T-Type Flip-Flops, " IEEE Jour. Of Solid-state Circ., Vol. 30, No. 1, pp. 19-24, January 1995.
49. [IIS89] H. Ichino, N. Ishihara, M. Suzuki, S. Konaka, "18-GHz 1/8 Dynamic Frequency Divider Using Si Bipolar Technologies, " IEEE Journal of Solid-State Circuits, vol. 24, no. 6, pp. 1723-1728, Dec. 1989.
50. [IIT95] K. Ishii, H. Ichino, M. Togashi, Y. Kobayashi, C. Yamaguchi "Very-High-Speed Si Bipolar Static Frequency Dividers with New T-Type Flip-Flops, " IEEE Jour. of Solid-State Circ., Vol. 30, No. 1, pp. 19-24, January 1995.
51. [JM97] D. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, 1997.
52. [JMS97] S. Jantzi, K. Martin, A. Sedra, "Quadrature bandpass modulator for digital radio, " IEEE Jour. of Solid-State Circuits, vol. 32, pp. 1935-1949, 1997.
53. [JR97] K. Jayabalan, S. Rezaul Hasan, "Current-mode BiCMOS folded source-coupled logic circuits, " Proc. of ISCAS'97, pp. 1880-1883, June 1997.
54. [K91] M. Kurisu, et al., "A Si Bipolar 21-GHz/320-mW Static Frequency Divider, " IEEE Jour. of Solid-state Circ., Vol. 26, No. 11, pp. 1626-1630, November 1991.
55. [K98] K. Koike, et al. "High-Speed, Low-Power, Bipolar Standard Cell Design Methodology for Gbit/s Signal Processing, " IEEE Jour. of Solid-state Circ., Vol. 33, No. 10, pp. 1536-1544, October 1998.
56. [KA92] S. Kiaei, D. Allstot, "Low-noise logic for mixed-mode VLSI circuits, " Microelectronics Journal, vol. 23, no. 2, pp. 103-114, Apr. 1992.
57. [KB92] G. K. Konstadinidis, H. H. Berger, "Optimization of Buffer Stages in Bipolar VLSI Systems, " IEEE Jour. of Solid-State Circ., Vol. 27, No. 7, pp. 1002-1013, July 1992.
58. [KBW01]H. Knapp, J. Bock, M. Wurzer, G. Ritzberger, K. Aufinger, L. Treitinger, "2-GHz/2-mW and 12-GHz/30-mW Dual-ModulusPrescalers in Silicon Bipolar Technology, " IEEE Jour. of Solid- State Circ., Vol. 36, No. 9, pp. 1420-1423, September 2001.
59. [KCA90] S. Kiaei, S. Chee, D. Allstot, "CMOS source-coupled logic for mixed-mode VLSI, " Proc. Int. Symp. Circuits Systems, pp. 1608- 1611, 1990.
60. [KDN91] B. Kup, E. Dijkmans, P. Naus, J. Sneep, "A bit-stream digital-toanalog converter with 18-b resolution, " IEEE Jour. of Solid-State Circuits, vol. 26, pp. 1757-1763, Dec. 1991.
61. [KH00] J. Kundan, S. Hasan, "Enhanced folded source-coupled logic technique for low-voltage mixed-signal integrated circuits, " IEEE Trans. on CAS - part II, vol. 47, no. 8, pp. 810-817, Aug. 2000.
62. [KH97] J. Kundan, S. Hasan, "Current mode BiCMOS folded sourcecoupled logic circuits, " Proc. of ISCAS'97, pp. 1880-1883, June 1997.
63. [KKI97] K. Kishine, Y. Kobayashi, H. Ichino, "A High-Speed, Low-Power Bipolar Digital Circuit for Gb/s LSI's: Current Mirror Control Logic, " IEEE Jour. of Solid-state Circ., Vol. 32, No. 2, pp. 215- 221, February 1997.
64. [KOS91] M. Kurisu, M. Ohuchi, A. Sawairi, M. Sugiyama, H. Takemura, T. Tashiro "A Si Bipolar 21-GHz/320-mW Static Frequency Divider, " IEEE Jour. of Solid-State Circ., Vol. 26, No. 11, pp. 1626-1630, November 1991.
65. [KUO92] M. Kurisu, G. Uemura, M. Ohuchi, C. Ogawa, H. Takemura, T. Morikawa, T. Tashiro "A Si Bipolar 28-GHz Dynamic Frequency Divider, " IEEE Jour. of Solid-State Circ., Vol. 27, No. 12, pp. 1799-1804w, November 1992.
66. [L95] Z. H. Lao, et al., "A 12 Gb/s Si Bipolar 4:1-Multiplexer IC for SDH Systems, " IEEE Jour. of Solid-state Circ., Vol. 30, No. 2, pp. 129-132, February 1995.
67. [L96] Z. Lao, et al., "Si Bipolar 14 Gb/s 1:4-Demultiplexer IC for System Applications, " IEEE Jour. of Solid-State Circ., Vol. 31, No. 1, pp. 54-59, January 1996.
68. [LHG84] H. Lee, D. Hodges, P. Gray, "A self-calibrating 15-bit CMOS A/D converter, " IEEE Jour. of Solid-State Circuits, vol. 19, pp. 813- 819, Dec. 1984.
69. [LL96] Z. Lao, U. Langmann, "Design of a Low-Power 10 Gb/s Si Bipolar 1:16-Demultiplexer IC, " IEEE Jour. of Solid-State Circ., Vol. 31, No. 1, pp. 128-131, January 1996.
70. [LR00] C. Lam, B. Razavi, "A 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-?m CMOS Technology, " IEEE Jour. of Solid-State Circ., Vol. 35, No. 5, pp. 788-794, May 2000.
71. [LS94] K. Laker, W. Sansen, Design of Analog Integrated Circuits and Systems, Mc Graw-Hill, 1994.
72. [LWO91]H. Leopold, G. Winkler, P. O'Leary, K. Ilzer, J. Jernej, "A monolithic CMOS 20-b analog-to-digital converter, " IEEE Jour. of Solid-State Circuits, vol. 26, pp. 910-916, July 1991.
73. [M89] R. Middlebrook, "Null Double Injection and the Extra Element Theorem", IEEE Trans. on Education, vol. 32, no. 3, pp. 167-180, August 1989.
74. [M92] S. Masui, "Simulation of substrate coupling in mixed-signal MOS circuits, " Proc. Of Symp. VLSI Circuits, pp. 42-43, 1992.
75. [M97] C. Maier, et al., "A 533-MHz BiCMOS Superscalar RISC Micorprocessor, " IEEE Jour. of Solid-state Circ., Vol. 32, No. 11, pp. 1625-1633, November 1997.
76. [M971] J. McNeill, "Jitter in Ring Oscillators, " IEEE Journal of Solid State Circuits, Vol. 32, No. 6, pp. 870-879, June 1997.
77. [MG87] J. Millman - A. Grabel, Microelectronics (Second Edition), McGraw-Hill, 1987.
78. [MK86] R. Muller, T. Kamins, Device Electronics for Integrated Circuits, John Wiley & Sons, 1986.
79. [MKA92]S. Maskai, S. Kiaei, D. Allstot, "Synthesis techniques for CMOS folded source-coupled logic circuits, " IEEE Jour. of Solid-State Circuits, vol. 27, no. 8, pp. 1157-1167, Aug. 1992.
80. [MSO92] M. Mizuno, H. Suzuki, M. Ogawa, K. Sato, H. Ichikawa, "A 3- mW 1.0-GHz Silicon-ECL Dual-Modulus Prescaler IC, " IEEE Jour. of Solid-State Circuits, vol. 27, no. 12, pp. 1794-1798, December 1992.
81. [NA97] H. Ng, D. Allstot, "CMOS current steering logic for low-voltage mixed-signal integrated circuits, " IEEE Trans. on VLSI Systems, vol. 5, no. 3, pp. 301-308, Sept. 1997.
82. [NIE03] H. Nosaka, K. Isshii, T. Enoki, T. Shibata, "A 10-Gb/s Data- Pattern Independent Clock and Data Recovery with a Two-Mode Phase Comparator, " IEEE Jour. of Solid-State Circuits, vol. 38, no. 2, pp. 192-197, February 2003.
83. [O99] V. Oklobdzija, High-Performance System Design (Circuits and Logic), IEEE Press 1999.
84. [P01] H. Partovi, "Clocked Storage Elements", in A. Chandrakasan, W. Bowhill, F. Fox, (Eds.), Design of High-Performance Microprocessor Circuits, IEEE Press 2001.
85. [PBS97] P. Poras, T. Balsara, D. Steiss, "Performance of CMOS differential circuits, " IEEE Jour. of Solid-State Circuits, vol. 31, pp. 841-846, June 1997.
86. [PM91] O. Pederson, K. Mayaram, Analog Integrated Circuits for Communication (principles, Simulation and Design), Kluwer Academic Publishers, 1991.
87. [R98] B. Razavi, RF Microelectronics, Prentice Hall, 1998.
88. [R96] J. Rabaey, Digital Integrated Circuits (A Design Perspective), Prentice Hall, 1996.
89. [R961] B. Razavi (Ed.), Monolithic Phase-Locked Loops and Clock Recovery Circuits (Theory and Design), IEEE Press 1996.
90. [R02] B. Razavi, "Prospect of CMOS Technology for High-Speed Optical Communication Circuits, " IEEE Jour. of Solid-State Circ., Vol. 37, No. 9, pp. 1135-1145, September 2002.
91. [RDR01] M. Reinhold, C. Dorschky, R. Pullela, P. Mayer, F. Kunz, Y. Beeyens, T. Link, J. Mattia, "A Fully Integrated 40-Gb/s Clock and Data Recovery IC With 1:4 DEMUX in SiGe Technology, " IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 1937-1945, Dec. 2001.
92. [RM96] H. Rein, M. Moller, "Design Considerations for Very-High-Speed Si-Bipolar IC's Operating up to 50 Gb/s, " IEEE Jour. of Solid- State Circ., Vol. 31, No. 8, pp. 1076-1090, August 1996.
93. [ROS94] B. Razavi, Y. Ota, R. Swartz, "Design techniques for low-voltage high speed digital bipolar circuits, " IEEE Jour. of Solid-State Circ., Vol. 29, No. 2, pp. 332-339, March 1994.
94. [RP96] J. Rabaey, M. Pedram (Eds.), Low power design methodologies, Kluwer Academic Publishers, 1996.
95. [S81] S. Sze, Physics of Semiconductor Devices, John Wiley & Sons, 1981.
96. [S02] R. Singh (Ed.), Signal Integrity Effects in Custom IC and ASIC Design, IEEE Press 2002.
97. [SD93] C. Stout, J. Doernberg, "10-Gb/s Silicon Bipolar 8:1 Multiplexer and 1:8 Demultiplexer, " IEEE Journal of Solid-State Circuits, vol. 28, no. 3, pp. 339-343, March 1993.
98. [SE94] K. M. Sharaf, M. Elmasry, "An Accurate Analytical Propagation Delay Model for High-Speed CML Bipolar Circuits, " IEEE Jour. of Solid-State Circ., Vol. 29, No. 1, pp. 31-45, January 1994.
99. [SE96] K. M. Sharaf, M. I. Elmasry, "Analysis and Optimization of Series- Gates CML and ECL High-Speed Bipolar Circuits, " IEEE Jour. of Solid-State Circ., Vol.31, No. 2, pp. 202-211, February 1996.
100. [SK97] R. Saez, M. Kayal, M. Declercq, M. Schneider, "Design guidelines for CMOS current steering logic, " Proc. of ISCAS'97, pp. 1872- 1875, 1997.
101. [SKD96] R. Sàez, M. Kayal, M. Declercq, M. Schneider, "Digital circuit techniques for mixed analog/digital circuits applications, " Proc. of ICECS'96, Rodos, Greece 1996.
102. [SL98] Shing-Tag Yan, H. Luong, "A 3-V 1.3-to-1.8-GHz CMOS Voltage-Controlled Oscillator with 0.3-ps Jitter, " IEEE Trans. on Circuits and Systems part II, Vol. 45, No. 7, pp. 876-880, July 1998.
103. [SLM93] D. Su, M. Loinaz, S. Masui, B. Wooley, "Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits, " IEEE Jour. of Solid-State Circuits, vol. 28, pp. 420-430, Apr. 1993.
104. [SP93] R. Senthinatan, J. Prince, "Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise, " IEEE Jour. of Solid-State Circuits, vol. 28, no. 12, pp. 1383-1388, Dec. 1993.
105. [S96] F. Sato, et al., "A 2.4 Gb/s Receiver and a 1:16 Demultiplexer in One Chip Using a Super Self-Aligned Selectively Grown SiGe Base (SSSB) Bipolar Transistor, " IEEE Jour. of Solid-State Circ., Vol. 31, No. 10, pp. 1451-1456, October 1996.
106. [SMS94] T. Seneff, L. McKay, K. Sakamoto, N. Tracht, "A Sub-1 mA 1.5- GHz Silicon Bipolar Dual Modulus Prescaler, " IEEE Jour. Of Solid-State Circ., Vol. 29, No. 10, pp. 1206-1211, October 1994.
107. [SMT98] G. Schuppener, M. Mokhtari, H. Tehnhunen, "A Divide-by-4 Circuit Implemented in Low Voltage, High Speed Topology, " Proc. ISCAS'98, Monterey, pp. 215-221, June 1998.
108. [SPM00] G. Schuppener, C. Pala, M. Mokhtari, "Investigation on Low- Voltage Low-Power Silicon Bipolar Design Topology for High- Speed Digital Circuits, " IEEE Jour. of Solid-State Circ., Vol. 35, No. 7, pp. 1051-1054, July 2000.
109. [SPW91] N. Sheng, R. Pierson, K. Wang, R. Nubling, P. Asbeck, M. Chang, W. Edwards, D. Phillips, "A High-Speed Multimodulus HBT Prescaler for Frequency Synthesizer Applications, " IEEE Jour. of Solid-State Circ., Vol. 26, No. 10, pp. 1362-1367, October 1991.
110. [SR01] J. Savoj, B. Razavi, High-Speed CMOS Circuits for Optical Receivers, Kluwer academic Publisher, 2001.
111. [SS91] A. Sedra, K. Smith, Microelectronic Circuits (third edition), Saunders College Publishing, 1991.
112. [SVR94] B. Stanistic, N. Verghese, R. Rutenbar, L. Carley, D. Allstot, "Addressing substrate coupling in mixed-mode IC's: Simulation and power distribution synthesis, " IEEE Jour. of Solid-State Circuits, vol. 29, pp. 226-238, Mar. 1994.
113. [T98] Y. Tsividis, Operation and modeling of MOS transistors, McGraw- Hill, 1998.
114. [T89] R. Treadway, "DC Analysis of Current Mode Logic, " IEEE Circuits and Device Magazine, pp. 21-35, March 1989.
115. [TS79] D. D. Tang, P. M. Solomon, "Bipolar Transistor Design for Optimized Power-Delay Logic Circuits, " IEEE Jour. of Solid-State Circ., Vol. SC-14, No. 4, pp. 679-684, August 1979.
116. [TUF01] A. Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okiara, H. Sakuraba, T. Endoh, F. Masuoka, "0.18-?m CMOS 10- Gb/s Multiplexer/Demultiplexer ICs Using Current Mode Logic with Tolerance to Threshold Voltage Fluctuation, " IEEE Jour. of Solid-State Circuits, vol. 36, no. 6, June 2001.
117. [VK95] C. Vaucher, D. Kasperkovitz, "A Wide-Band Tuning System for Fully Integrated Satellite Receivers, " IEEE Jour. of Solid-State Circ., Vol. 33, No. 7, pp. 987-997, July 1995.
118. [W90] G. Wilson, "Advances in Bipolar VLSI, " Proceeding of IEEE, Vol. 78 No. 11, pp. 1707-1719, November 1990.
119. [WKG94]T. Weigandt, B. Kim, P. Gray, "Analysis of Timing Jitter in CMOS Ring Oscillators, " IEEE Proc. ISCAS'94, London, pp. 27- 30, June 1994.
120. [YTC92] A. T. Yang, Y. Chang, "Physical Timing Modeling for Bipolar VLSI, " IEEE Jour. of Solid-State Circ., Vol. 27, No. 9, pp. 1245- 1254, September 1992.
121. [YEC83] P. Yang, B. Epler, P. Chatterjee, "An Investigation of the Charge Conservation Problem for MOSFET Circuit Simulation", IEEE Jour. of Solid-State Circuits, vo. 18, no. 1, pp. 128-138, February 1983.