Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 2, 1996, Pages 202-211

  Sharaf, Khaled M ^a,b,c   Elmasry, Mohamed I ^{a,b,d,e,f,g,h,i,j,k,l,m}  

^a UNIVERSITY OF WATERLOO   (Canada)

^b AinShams University ^*

^c AIN SHAMS UNIVERSITY   (Egypt)

^d CAIRO UNIVERSITY   (Egypt)

^e UNIVERSITY OF OTTAWA   (Canada)

^f NORTEL NETWORKS   (Canada)

^g VLSI Research Group

^h GENERAL ELECTRIC COMPANY   (United States)

ⁱ Unisys   (United States)

^j KUWAIT UNIVERSITY   (Kuwait)

^k Canadian Microelectron Corporation

^l Assoc of Prof Eng of Ontario

^m IEEE

more..

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS; ELECTRIC CURRENTS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; GATES (TRANSISTOR); MATHEMATICAL MODELS; OPTIMIZATION;

BIPOLAR CIRCUITS; CURRENT MODE LOGIC; EMITTER COUPLED LOGIC; HIGH CURRENT EFFECTS;

EMITTER COUPLED LOGIC CIRCUITS;

EID: 0030084277     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.487997     Document Type: Article

References (6)

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2. K. Runge et al., "Silicon bipolar integrated circuits for multi-Gb/s optical communication systems," IEEE J. Select. Areas Commun., vol. 9, pp. 636-646, June 1991.
3. K. G. Ashar, "The method of estimating delay in switching circuits and the figure of merit of a switching transistor,"IEEE Trans. Electron. Devices, vol. ED-11, pp. 497-506, Nov. 1964.
4. P. K. Tien, "Propagation delay in high speed silicon bipolar and GaAs HBT digital circuits," Int. J. High Speed Electron., vol. 1, pp. 101-124, 1990.
5. K. M. Sharaf and M. I. Elmasry, "An accurate analytical propagation delay model for high-speed CML bipolar circuits," IEEE J. Solid-State Circuits, vol. 29, pp. 31-45, Jan. 1994.
6. G. Konstadinidis and H. Berger, "Optimization of buffer stages in bipolar VLSI systems," IEEE J. Solid-State Circuits, vol. 27, pp. 1002-1013, July 1992.