Investigation on low-voltage low-power silicon bipolar design topology for high-speed digital circuits

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 7, 2000, Pages 1051-1054

  Schuppener, Gerd ^a   Pala, Costantino ^a   Mokhtari, Mehran ^a,b  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^b Hughes Aircraft Co   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; SEMICONDUCTING SILICON;

LOW-VOLTAGE LOW-POWER SILICON BIPOLAR DESIGN TOPOLOGY;

BIPOLAR INTEGRATED CIRCUITS;

EID: 0034225503     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.848216     Document Type: Article

References (5)

1. H.-M. Rein and M. Möller, "Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s," IEEE J. Solid-State Circuits, vol. 31, pp. 1076-1090, Aug. 1996.
2. K. Kishine, Y. Kobayashi, and H. Ichino, "A high-speed, low-power bipolar digital circuit for Gb/s LSI's: Current mirror control logic," IEEE J. Solid-State Circuits, vol. 32, pp. 215-221, Feb. 1997.
3. G. Schuppener, M. Mokhtari, and H. Tenhunen, "A divide-by-4 circuit implemented in low voltage, high speed topology," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS'98), Monterey, CA, June 1998.
4. K. Kamura. "Circuit design techniques for very low-voltage analog functional blocks using triple-tail cells," IEEE Trans. Circuits and Sysr. - I, vol. 42, pp. 873-885, Nov. 1995.
5. B. Razavi, Y. Ota. and R. G. Swartz, "Design techniques for low-voltage high-speed digital bipolar circuits," IEEE J. Solid-State Circuits, vol. 29, pp. 332-339. Mar. 1994.