A 533-MHz BiCMOS superscalar RISC microprocessor

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 11, 1997, Pages 1625-1633

  Maier, Cliff A ^a,b,c,m   Markevitch, James A ^a,b,d,n,o   Brashears, Cheryl Senter ^b,c   Sippel, Tim ^a,b,e   Cohen, Earl T ^b,f   Blomgren, Jim ^b,g   Ballard, James G ^b,h   Pattin, Jay ^b,i   Moldenhauer, Viki ^b,j   Thomas, Jeffrey A ^a,b,k   Taylor, George ^b,l  

^a IEEE   (United States)

^b Exponential Technology   (United States)

^c ADVANCED MICRO DEVICES   (United States)

^d Evergreen Technology   (United States)

^e Alchemy Designs   (United States)

^f BiT Microsystems   (United States)

^g EVSX   (United States)

^h SUN MICROSYSTEMS   (United States)

ⁱ Epigram   (United States)

^j PHILIPS RESEARCH LABORATORIES   (Germany)

^k DEC   (United States)

^l Rensselaer Polytechnic Institute ^*

^m RENSSELAER POLYTECHNIC INSTITUTE   (United States)

ⁿ MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^o LAWRENCE LIVERMORE NATIONAL LABORATORY   (United States)

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Author keywords

BiCMOS integrated circuits; Bipolar digital integrated circuits; Emitter coupled logic; Microprocessors

Indexed keywords

BIPOLAR TRANSISTORS; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; DIES; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; REDUCED INSTRUCTION SET COMPUTING; VLSI CIRCUITS;

EMITTER COUPLED LOGIC; POWERPC ARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 0031273104     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.641683     Document Type: Article

References (8)

1. IBM, The PowerPC Architecture, 2nd ed. San Francisco, CA: Morgan Kaufmann, Dec. 13, 1994.
2. E. T. Cohen et al., "A 533MHz BiCMOS Superscalar Microprocessor," in 1997 Dig. Tech. Papers, IEEE Solid State Circuits Conf., 1997, pp. 164-165.
3. PowerPC 60x Microprocessor Interface Specification, Version 3.0, Motorola Inc., Mar. 28, 1994.
4. T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Trans. Electronic Devices, vol. 40, pp. 118-124, Jan. 1993.
5. F. Dartu and L. Pileggi, "Calculating worst-case gate delays due to dominant capacitance coupling," in Proc. 1997 Design Automation Conf., June 1997, pp. 46-51.
6. IEEE Standard 1149.1-1990, "IEEE standard test access port and boundary scan architecture," May 21, 1990.
7. H. Chang and J. A. Abraham, "Delay test techniques for boundary scan based architectures," in Proc., Custom Integrated Circuits Conf., 1992, pp. 13.2.1-13.2.4.
8. C. A. Maier et al., "Embedded at-speed testing schemes with low overhead for high speed digital systems on multi-chip modules," in IEEE Innovative Systems in Silicon Conf., Austin, TX, Oct. 8-10, 1996, pp. 210-216.