A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 2, 2003, Pages 192-197

  Nosaka, Hideyuki ^a   Ishii, Kiyoshi ^a   Enoki, Takatomo ^a   Shibata, Tsugumichi ^a  

^a NTT CORPORATION   (Japan)

Author keywords

Clock and data recovery (CDR); Consecutive identical digit (CID); Jitter generation; Jitter tolerance; Jitter transfer; Phase locked loop (PLL)

Indexed keywords

FLIP FLOP CIRCUITS; JITTER; PHASE COMPARATORS; PHASE LOCKED LOOPS;

CONSECUTIVE IDENTICAL DIGITS (CID);

INTEGRATED CIRCUITS;

EID: 0037321173     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.807408     Document Type: Article

References (7)

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