-
2
-
-
0001775617
-
A 52 and 155 MHz clock-recovery PLL
-
L. DeVito, J. Newton, R. Croughwell, J. Bulzacchelli, and F. Benkley, "A 52 and 155 MHz clock-recovery PLL," in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 142-143.
-
(1991)
ISSCC Dig. Tech. Papers, Feb.
, pp. 142-143
-
-
DeVito, L.1
Newton, J.2
Croughwell, R.3
Bulzacchelli, J.4
Benkley, F.5
-
3
-
-
0026972926
-
A 6-GHz integrated phase-locked loop using AlCaAs/Ga/As heterojunction bipolar transistors
-
Dec.
-
A. W. Buchwald, K. W. Martin, A. K. Oki, and K. W. Kobayashi, "A 6-GHz integrated phase-locked loop using AlCaAs/Ga/As heterojunction bipolar transistors," IEEE J. Solid-State Circuits, vol. 27, pp. 1752-1762, Dec. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 1752-1762
-
-
Buchwald, A.W.1
Martin, K.W.2
Oki, A.K.3
Kobayashi, K.W.4
-
4
-
-
0005159208
-
A monolithic 622 Mb/s clock extraction data retiming circuit
-
Feb.
-
B. Lai and R. C. Walker, "A monolithic 622 Mb/s clock extraction data retiming circuit," in ISSCC Dig. Tech. Papers, Feb. 1993, pp. 144-144.
-
(1993)
ISSCC Dig. Tech. Papers
, pp. 144-144
-
-
Lai, B.1
Walker, R.C.2
-
5
-
-
0031629517
-
A 0.4 mm CMOS 10 Gb/s 4-PAM pre-emphasis serial link transmitter
-
June
-
R. Farjad-Rad, C. K. Yang, M. Horowitz, and T. H. Lee, "A 0.4 mm CMOS 10 Gb/s 4-PAM pre-emphasis serial link transmitter," in Symp. VLSI Circuits Dig. Tech Papers, June 1998, pp. 198-199.
-
(1998)
Symp. VLSI Circuits Dig. Tech Papers
, pp. 198-199
-
-
Farjad-Rad, R.1
Yang, C.K.2
Horowitz, M.3
Lee, T.H.4
-
6
-
-
0024133995
-
A 33 Mbi/s data synchronizing phase-locked loop circuit
-
Feb.
-
W. D. Llewellyn, M. M. H. Wong, G. W. Tietz, and P. A. Tucci, "A 33 Mbi/s data synchronizing phase-locked loop circuit," in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 12-13.
-
(1988)
ISSCC Dig. Tech. Papers
, pp. 12-13
-
-
Llewellyn, W.D.1
Wong, M.M.H.2
Tietz, G.W.3
Tucci, P.A.4
-
7
-
-
0345475572
-
A two-chip CMOS read channel for hard-disk drives
-
Feb.
-
M. Negahban, R. Behrasi, G. Tsang, H. Abouhossein, and G. Bouchaya, "A two-chip CMOS read channel for hard-disk drives," in ISSCC Dig. Tech. Papers, Feb. 1993, pp. 216-217.
-
(1993)
ISSCC Dig. Tech. Papers
, pp. 216-217
-
-
Negahban, M.1
Behrasi, R.2
Tsang, G.3
Abouhossein, H.4
Bouchaya, G.5
-
8
-
-
0024091885
-
A variable delay line PLL for CPU-coprocessor synchronization
-
Oct.
-
M. G. Johnson and E. L. Hudson, "A variable delay line PLL for CPU-coprocessor synchronization," IEEE J. Solid-State Circuits, vol. 23, pp. 1218-1223, Oct. 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.23
, pp. 1218-1223
-
-
Johnson, M.G.1
Hudson, E.L.2
-
9
-
-
0026954972
-
A PLL clock generator with 5-110 MHz of lock range for microprocessors
-
Nov.
-
I. A. Young, J. K. Greason, and K. L. Wong, "A PLL clock generator with 5-110 MHz of lock range for microprocessors," IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, Nov. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 1599-1607
-
-
Young, I.A.1
Greason, J.K.2
Wong, K.L.3
-
10
-
-
0029289178
-
A wide-bandwidth low-voltage PLL for PowerPC™ microprocessors
-
Apr.
-
J. Alvarez, H. Sanchez, G. Gerosa, and R. Countryman, "A wide-bandwidth low-voltage PLL for PowerPC™ microprocessors," IEEE J. Solid-State Circuits, vol. 30, pp. 383-391, Apr. 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, pp. 383-391
-
-
Alvarez, J.1
Sanchez, H.2
Gerosa, G.3
Countryman, R.4
-
11
-
-
0342886911
-
A PLL clock generator with 5-110 MHz lock range for microprocessors
-
Feb.
-
I. A. Young, J. K. Greason, J. E. Smith, and K. L. Wong, "A PLL clock generator with 5-110 MHz lock range for microprocessors," in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 50-51.
-
(1992)
ISSCC Dig. Tech. Papers
, pp. 50-51
-
-
Young, I.A.1
Greason, J.K.2
Smith, J.E.3
Wong, K.L.4
-
12
-
-
84986332214
-
PLL design for a 500 Mb/s interface
-
Feb.
-
M. Horowitz, A. Chen, J. Cobrunson, J. Gasbarro, T. Lee, W. Leung, W. Richardson, T. Thrush, and Y. Fujii, "PLL design for a 500 Mb/s interface," in ISSCC Dig. Tech. Papers, Feb. 1993, pp. 160-161.
-
(1993)
ISSCC Dig. Tech. Papers
, pp. 160-161
-
-
Horowitz, M.1
Chen, A.2
Cobrunson, J.3
Gasbarro, J.4
Lee, T.5
Leung, W.6
Richardson, W.7
Thrush, T.8
Fujii, Y.9
-
13
-
-
0002313494
-
Analysis of timing jitter in CMOS ring oscillators
-
June
-
T. C. Weigandt, B. Kim, and P. R. Gray, "Analysis of timing jitter in CMOS ring oscillators," in Proc. ISCAS, June 1994.
-
(1994)
Proc. ISCAS
-
-
Weigandt, T.C.1
Kim, B.2
Gray, P.R.3
-
14
-
-
0031165398
-
Jitter in ring oscillators
-
June
-
J. McNeill, "Jitter in ring oscillators," IEEE J. Solid-State Circuits, vol. 32, pp. 870-879, June 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, pp. 870-879
-
-
McNeill, J.1
-
15
-
-
0030105412
-
A study of phase noise in CMOS oscillators
-
Mar.
-
B. Razavi, "A study of phase noise in CMOS oscillators," IEEE J. Solid-State Circuits, vol. 31, pp. 331-343, Mar. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 331-343
-
-
Razavi, B.1
-
16
-
-
0031644631
-
Phase noise in multigigahertz CMOS ring oscillators
-
May
-
A. Hajimiri, S. Limotyrakis, and T. H. Lee, "Phase noise in multigigahertz CMOS ring oscillators," in Proc. Custom Integrated Circuits Conf., May 1998, pp. 49-52.
-
(1998)
Proc. Custom Integrated Circuits Conf.
, pp. 49-52
-
-
Hajimiri, A.1
Limotyrakis, S.2
Lee, T.H.3
-
17
-
-
0032002580
-
A general theory of phase noise in electrical oscillators
-
Feb.
-
A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, Feb. 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, pp. 179-194
-
-
Hajimiri, A.1
Lee, T.H.2
-
19
-
-
0022811203
-
High-frequency noise measurements of FET's with small
-
dimensions Nov.
-
A. A. Abidi, "High-frequency noise measurements of FET's with small dimensions," IEEE Trans. Electron Devices, vol. ED-33, pp. 1801-1805, Nov. 1986.
-
(1986)
IEEE Trans. Electron Devices
, vol.ED-33
, pp. 1801-1805
-
-
Abidi, A.A.1
-
20
-
-
0029226688
-
Inductorless oscillator design for personal communications devices - A 1.2 μm CMOS process case study
-
May
-
T. Kwasniewski, M. Abou-Seido, A. Bouchet, F. Gaussorgues, and J. Zimmerman, "Inductorless oscillator design for personal communications devices - A 1.2 μm CMOS process case study," in Proc. CICC, May 1995, pp. 327-330.
-
(1995)
Proc. CICC
, pp. 327-330
-
-
Kwasniewski, T.1
Abou-Seido, M.2
Bouchet, A.3
Gaussorgues, F.4
Zimmerman, J.5
-
21
-
-
0027851095
-
Precise delay generation using coupled oscillators
-
Dec.
-
J. G. Maneatis and M. A. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273-1282, Dec. 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, pp. 1273-1282
-
-
Maneatis, J.G.1
Horowitz, M.A.2
|