Performance evaluation of the low-voltage CML D-latch topology

Integration, the VLSI Journal

Volumn 36, Issue 4, 2003, Pages 191-209

  Alioto, Massimo ^a   Mita, R ^b   Palumbo, G ^b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

Author keywords

Bipolar; Current mode logic; High speed; Latch; Low voltage

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; BIPOLAR TRANSISTORS; ELECTRIC POTENTIAL; MOBILE TELECOMMUNICATION SYSTEMS; SATELLITES; TOPOLOGY;

POWER-DELAY INTERDEPENDENCE;

EMITTER COUPLED LOGIC CIRCUITS;

EID: 0344875062     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2003.09.001     Document Type: Article

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