Design of MUX, XOR and D-latch SCL gates

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  Alioto, M ^a   Palumbo, G ^b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS;

POWER CONSUMPTION;

LOGIC GATES;

EID: 0037744581     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A. Tanabe et al., "0.18-μm CMOS 10-Gb/s Multiplexer/Demultiplexer ICs Using Current Mode Logic with Tolerance to Threshold Voltage Fluctuation," IEEE J. of Solid-State Circuits, vol. 36, no. 6, June 2001.
2. L. Andersson et al., "Silicon Bipolar Chipset for SONET/SDH 10 Gb/s Fiber-Optic Communication Links," IEEE J. of Solid-State Circuits, vol. 30, no. 3, march 1995.
3. M. Alioto, G. Palumbo, "Power-Delay Trade-Offs in SCL Gates," Proc. of ISCAS2002, pp. III/249-252, Phoenix (USA), May 2002.
4. M. Alioto, G. Palumbo, S. Pennisi, "Modeling of Source Coupled Logic Gates," International Journal of Circuit Theory and Applications, vol. 30, no. 4, pp.459-477, July 2002.
5. J. Rabaey, Digital Integrated Circuits (A Design Perspective), Prentice Hall, 1996.
6. J.B. Cochrun, A. Grabel, "A Method for the Determination of the Transfer Function of Electronic Circuits", IEEE Trans. on Circuit Theory, vol. CT-20, no. 1, pp. 16-20, Jan. 1973.