Design strategies for source coupled logic gates

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 50, Issue 5, 2003, Pages 640-654

  Alioto, Massimo ^a,b   Palumbo, Gaetano ^a  

^a UNIVERSITY OF CATANIA   (Italy)

^b UNIVERSITY OF SIENA   (Italy)

Author keywords

Analytical delay model; Source coupled logic (SCL) gates

Indexed keywords

BUFFER CIRCUITS; COMPUTER SIMULATION; COUPLED CIRCUITS; ELECTRIC CURRENTS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LOGIC CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION; TRANSISTORS;

COUPLED LOGIC GATES; POWER DISSIPATION;

LOGIC GATES;

EID: 0037899025     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2003.811023     Document Type: Article

References (38)

1. B. Del Signore, D. Kerth, N. Sooch, and E. Swanson, "A monolithic 20-b delta-sigma A/D converter," IEEE J. Solid-State Circuits, vol. 25, pp. 1311-1317, Dec. 1990.
2. H. Leopold, G. Winkler, P. O'Leary, K. Ilzer, and J. Jernej, "A monolithic CMOS 20-b analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 26, pp. 910-916, July 1991.
3. I. Fujimori et al., "A 5-V single chip delta-sigma audio A/D converter with 111 dB dynamic range," IEEE J. Solid-State Circuits, vol. 32, pp. 329-336, Mar. 1997.
4. S. Jantzi, K. Martin, and A. Sedra, "Quadrature bandpass ΣΔ modulator for digital radio," IEEE J. Solid-State Circuits, vol. 32, pp. 1935-1949, 1997.
5. B. Kup, E. Dijkmans, P. Naus, and J. Sneep, "A bit-stream digital-to-analog converter with 18-b resolution," IEEE J. Solid-State Circuits, vol. 26, pp. 1757-1763, Dec. 1991.
6. D. Su, M. Loinaz, S. Masui, and B. Wooley, "Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits," IEEE J. Solid-State Circuits, vol. 28, pp. 420-430, Apr. 1993.
7. S. Masui, "Simulation of substrate coupling in mixed-signal MOS circuits," in Proc. Symp. VLSI Circuits, 1992, pp. 42-43.
8. B. Stanistic, N. Nerghese, R. Rutenbar, L. Carley, and D. Allstot, "Addressing substrate coupling in mixed-mode ICs: Simulation and power distribution synthesis," IEEE J. Solid-State Circuits, vol. 29, pp. 226-238, Mar. 1994.
9. J. Rabaey and M. Pedram, Eds., Low Power Design Methodologies. Norwell, MA: Kluwer, 1996.
10. H. Lee, D. Hodges, and P. Gray, "A self-calibrating 15-bit CMOS A/D converter," IEEE J. Solid-State Circuits, vol. 19, pp. 813-819, Dec. 1984.
11. D. Allstot, S. Chee, S. Kiaei, and M. Shristawa, "Folded source-coupled logic versus. CMOS static logic for low-noise mixed-signal ICs," IEEE Trans. Circuits Syst. I, vol. 40, pp. 553-563, Sept. 1993.
12. S. Kiaei, S. Chee, and D. Allstot, "CMOS source-coupled logic for mixed-mode VLSI," in Proc. Int. Symp. Circuits Systems, 1990, pp. 1608-1611.
13. S. Kiaei and D. Allstot, "Low-noise logic for mixed-mode VLSI circuits," Microelectron. J., vol. 23, no. 2, pp. 103-114, 1992.
14. S. Maskai, S. Kiaei, and D. Allstot, "Synthesis techniques for CMOS folded source-coupled logic circuits," IEEE J. Solid-State Circuits, vol. 27, pp. 1157-1167, Aug. 1992.
15. R. Senthinatan and J. Prince, "Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise," IEEE J. Solid-State Circuits, vol. 28, pp. 1383-1388, Dec. 1993.
16. S. Embabi, D. Brueske, and K. Rachamreddy, "A BiCMOS low-power current mode gate," IEEE J. Solid-State Circuits, vol. 29, pp. 741-745, June 1994.
17. C. Choy, C. Chan, and M. Ku, "A feedback control circuit design technique to suppress power noise in high speed output driver," in Proc. ISCAS'95, Apr. 1995, pp. 307-310.
18. R. Sàez, M. Kayal, M. Declercq, and M. Schneider, "Digital circuit techniques for mixed analog/digital circuits applications," in Proc. ICECS'96, Rodos, Greece, 1996.
19. P. Poras, T. Balsara, and D. Steiss, "Performance of CMOS differential circuits," IEEE J. Solid-State Circuits, vol. 31, pp. 841-846, June 1997.
20. J. Kundan and S. Hasan, "Current mode BiCMOS folded source-coupled logic circuits," in Proc. ISCAS'97, June 1997, pp. 1880-1883.
21. K. Jayabalan and S. R. Hasan, "Current-mode BiCMOS folded source-coupled logic circuits," in Proc. ISCAS'97, June 1997, pp. 1880-1883.
22. C. Choy, C. Chan, M. Ku, and J. Povazanec, "Design procedure of low-noise high-speed adaptive output drivers," in Proc. ISCAS'97, 1997, pp. 1796-1799.
23. R. Saez, M. Kayal, M. Declercq, and M. Schneider, "Design guidelines for CMOS current steering logic," in Proc. ISCAS'97, 1997, pp. 1872-1875.
24. H. Ng and D. Allstot, "CMOS current steering logic for low-voltage mixed-signal integrated circuits," IEEE Trans. VLSI Syst., vol. 5, pp. 301-308, Sept. 1997.
25. J. Kundan and S. Hasan, "Enhanced folded source-coupled logic technique for low-voltage mixed-signal integrated circuits," IEEE Trans. Circuits Syst. II, vol. 47, pp. 810-817, Aug. 2000.
26. Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User's Guide. Boston, MA: Kluwer, 1999.
27. M. Alioto, G. Palumbo, and S. Pennisi, "Modeling of source coupled logic gates," Int. J. Circuit Theory Applicat., vol. 30, no. 4, pp. 459-477, 2002.
28. B. Cochrun and A. Grabel, "A method for the determination of the transfer function of electronic circuits," IEEE Trans. Circuit Theory, vol. CT-20, pp. 16-20, Jan. 1973.
29. J. Rabaey, Digital Integrated Circuits (A Design Perspective). Englewood Cliffs, NJ: Prentice-Hall, 1996.
30. P. Yang, B. Epler, and P. Chatterjee, "An investigation of the charge conservation problem for MOSFET circuit simulation," IEEE J. Solid-State Circuits, vol. 18, pp. 128-138, Feb. 1983.
31. Y. Tsividis, Operation and Modeling of MOS Transistors. New York: McGraw-Hill, 1998.
32. K. Laker and W. Sansen, Design of Analog Integrated Circuits and Systems. New York: McGraw-Hill, 1994.
33. A. Sedra and K. Smith, Microelectronic Circuits. Philadelphia, PA: Saunders, 1989.
34. P. Vasudew and P. Zeitzoff, "Si-ULSI with a scaled-down future," IEEE Circuits Devices Mag., vol. 13, pp. 19-29, Mar. 1998.
35. Q. Huang, F. Piazza, P. Orsetti, and T. Ohguro, "The impact of scaling down to deep submicron on CMOS RF circuits," IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 1023-1036, July 1988.
36. H. Iwai, "CMOS technology - year 2010 and beyond," IEEE J. Solid-State Circuits, vol. 34, pp. 357-36, Mar. 1999.
37. D. Critchlow, "MOSFET scaling - the driver of VLSI technology," Proc. IEEE, vol. 87, pp. 659-666, Apr. 1999.
38. H. Wong, D. Frank, P. Solomon, C. Wann, and J. Welser, "Nanoscale CMOS," Proc. IEEE, vol. 87, pp. 537-570, Apr. 1999.