Design of monolithic phase-locked loops and clock recovery circuits-a tutorial

Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design

Volumn , Issue , 1996, Pages 1-39

  Razavi, Behzad ^a  

^a NONE

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EID: 84940468386     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1109/9780470545331.ch1     Document Type: Chapter

References (35)

1. F. M. Gardner. Phaselock Techniques, Second Edition. New York: Wiley & Sons, 1979.
2. A. B. Grebene, “The monolithic phase locked loop-A versatile building block," IEEE Spectrum, vol. 8, pp. 38-49, March 1971.
3. R. E. Best. Phase-Locked Loops, Second Edition. New York: McGraw-Hill, 1993.
4. G. S. Moschytz, “Miniaturized RC filters using phase-locked loop," Bell Syst. Tech. J., vol. 44, pp. 823-870, May 1965.
5. W. F. Egan. Frequency Synthesis by Phase Lock. New York: Wiley & Sons, 1981.
6. M. Bazes, “A novel precision MOS synchronous delay line," IEEE J. Solid-State Circuits, vol. 20, pp. 1265-1271, December 1985.
7. M. G. Johnson and E. L. Hudson, “A variable delay line PLL for CPU-coprocessor synchronization," IEEE J. Solid-State Circuits, vol. 23, pp. 1218-1223, October 1988.
8. J. Sonntag and R. Leonowich, “A monolithic CMOS 10 MHz DPLL for burst-mode data retiming," ISSCC Dig. Tech. Papers, pp. 194-195, San Francisco, CA, February 1990.
9. B. van der Pol, “The nonlinear theory of electric oscillators," Proc. IRE, vol. 22, pp. 1051-1086, September 1934.
10. A. Borys, “Elementary deterministic theories of frequency and amplitude stability in feedback oscillators," IEEE Trans., Circuits Syst., vol. 34, pp. 254-258, March 1987.
11. B. Razavi, “Analysis, modeling, and simulation of phase noise in monolithic voltage-controlled oscillators," Proc. CICC, pp. 323-326, Santa Clara, CA, 1995.
12. B. Lai and R. C. Walker, “A monolithic 622 Mb/sec clock extraction and data retiming circuit," ISSCC Dig. Tech. Papers, pp. 144-145, San Francisco, CA, February 1991.
13. S. K. Enam and A. A. Abidi, “NMOS ICs for clock and data regeneration in gigabit-per-second optical-fiber receivers," IEEE J. Solid-State Circuits, vol. 27, pp. 1763-1774, December 1992.
14. A. Pottbacker and U. Langmann, “An 8 GHz silicon bipolar clock recovery and data regenerator IC," IEEE J. Solid-State Circuits, vol. 29, pp. 1572-1576, December 1994.
15. B. Razavi and J. Sung, “A 2.5-Gb/sec 15-mW BiCMOS clock recovery circuit," Symp. VLSI Circuits Dig. Tech. Papers, pp. 83-84, Kyoto, Japan, 1995.
16. C. A. Sharpe, “A 3-state phase detector can improve your next PLL design," EDN, pp. 55-59, September 20, 1976.
17. I. Shahriary et al., “GaAs monolithic phase/frequency discriminator," IEEE GaAs IC Symp. Dig. Tech. Papers, pp. 183-186, 1985.
18. I. A. Young, J. K. Greason, and K. L. Wong, “A PLL clock generator with 5 to 110 MHz of lock range for microprocessors," IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, November 1992.
19. D. K. Jeong et al., “Design of PLL-based clock generation circuits," IEEE J. Solid-State Circuits, vol. 22, pp. 255-261, April 1987.
20. F. M. Gardner, “Charge-pump phase-locked loops," IEEE Trans. Comm., vol. COM-28, pp. 1849-1858, November 1980.
21. B. Razavi. Principles of Data Conversion System Design. Piscataway, NJ: IEEE Press, 1995.
22. D. Mijuskovic et al., “Cell-based fully integrated CMOS frequency synthesizers," IEEE J. Solid-State Circuits, vol. 29, pp. 271-279, March 1994.
23. I. Novof et al., “Fully-integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 psec jitter," ISSCC Dig. Tech. Papers, pp. 112-113, San Francisco, CA, February 1995.
24. V. F. Kroupa, “Noise properties of PLL systems," IEEE Trans. Comm., vol. COM-30, pp. 2244-2252, October 1982.
25. S. K. Shanmugam. Digital and Analog Communication Systems. New York: Wiley & Sons, 1979.
26. A. Pottbacker, U. Langmann, and H. U. Schreiber, “A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s " IEEE J. Solid-State Circuits, vol. 27, pp. 1747-1751, December 1992.
27. D. Richman, “Color-carrier reference phase synchronization accuracy in NTSC color television," Proc. IRE, vol. 42, pp. 106-133, January 1954.
28. J. A. Bellisio, “A new phase-locked loop timing recovery method for digital regenerators," IEEE Int. Communications Conf. Rec, vol. 1, June 1976, pp. 10-17-10-20.
29. F. M. Gardner, “Properties of frequency difference detectors," IEEE Trans. Comm., vol. COM-33, pp. 131-138, February 1985.
30. D. G. Messerschmitt, “Frequency detectors for PLL acquisition in timing and carrier recovery," IEEE Trans. Comm., vol. COM-27, pp. 1288-1295, September 1979.
31. C. R. Hogge, “A self-correcting clock recovery circuit," IEEE J. Lightwave Technology, vol. LT-3, pp. 1312-1314, December 1985.
32. L. De Vito et al., “A 52 MHz and 155 MHz clock recovery PLL," ISSCC Dig. Tech. Papers, pp. 142-143, San Francisco, CA, February 1991.
33. T. H. Lee and J. F. Bulzacchelli, “A 155-MHz clock recovery delay- and phase-locked loop," IEEE J. Solid-State Circuits, vol. 27, pp. 1736-1746, December 1992.
34. J. Alvarez et al., “A wide-bandwidth low-voltage PLL for PowerPC microprocessors," IEEE J. Solid-State Circuits, vol. 30, pp. 383-391, April 1995.
35. J. A. Crawford. Frequency Synthesizer Design Handbook. Norwood, MA: Artech House, 1994.