A fully integrated 40-Gb/s clock and data recovery IC with 1:4 DEMUX in SiGe Technology

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 12, 2001, Pages 1937-1945

  Reinhold, Mario ^a   Dorschky, Claus ^a   Rose, Eduard ^a   Pullela, Rajasekhar ^b   Mayer, Peter ^c   Kunz, Frank ^a   Baeyens, Yves ^d,e   Link, Thomas ^c   Mattia, John Paul ^f  

^a Cisco CoreOptics GmbH   (Germany)

^b Gtran Inc   (United States)

^c NOKIA RESEARCH CENTER   (United States)

^d IEEE

^e LUCENT TECHNOLOGIES   (United States)

^f Big Bear Networks   (United States)

Author keywords

Bang bang; BER; CDR; Clock and data recovery; Demultiplexer; DEMUX; Dynamic frequency divider; Jitter generation; Jitter tolerance; Limiting amplifier; OSNR; Phase detector; Phase locked loop; PLL; SiGe; VCO

Indexed keywords

AMPLIFIERS (ELECTRONIC); BIT ERROR RATE; DEMULTIPLEXING; FREQUENCY DIVIDING CIRCUITS; HETEROJUNCTION BIPOLAR TRANSISTORS; INTEGRATED CIRCUIT MANUFACTURE; JITTER; OPTICAL LINKS; PHASE LOCKED LOOPS; PHASE MEASUREMENT; SEMICONDUCTING SILICON COMPOUNDS; SIGNAL TO NOISE RATIO;

CLOCK AND DATA RECOVERY INTEGRATED CIRCUITS; DEMULTIPLEXER FUNCTIONALITY; DYNAMIC FREQUENCY DIVIDER; OPTICAL SIGNAL-TO-NOISE RATIO; PHASE DETECTOR; SILICON GERMANIUM;

TIMING CIRCUITS;

EID: 0035690864     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.972144     Document Type: Article

References (10)

1. max and 11-ps gate delay
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4. A plastic packaged 10-Gb/s BiCMOS clock and data recovery 1:4-demultiplexer with external VCO
5. Clock recovery from random binary signals
6. T silicon bipolar technology
7. 42-GHz static frequency divider in a Si/SiGe bipolar technology
8. 55-GHz dynamic frequency divider IC
9. Design considerations for very-high-speed Si-bipolar ICs operating up to 50-Gb/s