Design of a low-power 10 Gb/s Si bipolar 1 : 16-demultiplexer IC

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 1, 1996, Pages 128-131

  Lao, Zhihao ^a   Langmann, Ulrich ^a  

^a RUHR UNIVERSITY BOCHUM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR SEMICONDUCTOR DEVICES; ELECTRIC CURRENTS; FLIP FLOP CIRCUITS; RESISTORS; SEMICONDUCTING SILICON; TIMING DEVICES; TRANSISTORS;

COMMON MODE REJECTION RATIO; DECODING EFFECTS; DEMULTIPLEXER; LOAD RESISTOR; LOGIC FUNCTION; SYNCHRONOUS DIGITAL HIERARCHY; SYNCHRONOUS OPTICAL NETWORKS;

OPTICAL COMMUNICATION EQUIPMENT;

EID: 0029734513     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.485875     Document Type: Article

References (6)

1. Z. H. Lao, U. Langmann, J. N. Albers, E. Schlag, and D. Clawin, "Silicon bipolar 14 Gb/s 1 : 4-demultiplexer IC regarding system requirements," in IEEE 1994 BCTM, Dig. Tech. Pap., Minneapolis, MN, pp. 103-106.
2. Z. H. Lao, J. N. Albers, U. Langmann, and E. Schlag, "A 20 Gb/s silicon bipolar 1 : 4-demultiplexer IC," IEEE J. Lightwave Technol., vol. 12, no. 2, pp. 320-324, Feb. 1994.
3. C. L. Stout and J. Doernberg, "10-Gb/s Silicon bipolar 8 : 1 multiplexer and 1 : 8 demultiplexer," IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 339-343, Mar. 1993.
4. H. Sato, K. Ueda, N. Sasaki, T. Ikeda, and K. Mashiko, "A voltage compensated series-gate bipolar circuit operating at sub-2 V," IEEE J. Solid-State Circuits, vol. 29, no. 10, pp. 1200-1205, Oct. 1994.
5. W. Wihelm and P. Weger, "2 V Low-power bipolar logic," in 1994 Int. Solid-State Circuits Conf., Dig. Tech. Pap., 1994, pp. 94-95.
6. W. M. Huang, C. I. Drowley, P. J. Vande Voorde, D. Pettengill, J. E. Turner, A. K. Kapoor, C.-H. Lin et al., "A high-speed bipolar technology featuring self-aligned single-poly base and submicrometer emitter contacts," IEEE Electron Device Lett., vol. 11, no. 9, pp. 412-414, Sept. 1990.