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Volumn 33, Issue 10, 1998, Pages 1572-1575

A 723-MHz 17.2-mW CMOS programmable counter

Author keywords

CMOS digital integrated circuits; Flip flop circuits; Logic design; Phase locked loops; Programmable circuits

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED LOGIC DESIGN; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; FREQUENCY DIVIDING CIRCUITS; PHASE LOCKED LOOPS;

EID: 0032187836     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.720407     Document Type: Article
Times cited : (27)

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    • Chang, B.1    Park, J.2    Kim, W.3
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    • 0030188644 scopus 로고    scopus 로고
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    • J. Craninckx and M. Steyaert, "A 1.75-GHz/3-V dual-modulus divide-by-128/129 pre-scalar in 0.7-μm CMOS," IEEE J Solid-State Circuits, vol. 31, pp. 890-897, Feb. 1996.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.