Modeling and optimized design of current mode MUX/XOR and D flip-flop

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 47, Issue 5, 2000, Pages 452-461

  Alioto, M ^a   Palumbo, G ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; COMPUTER SIMULATION; EMITTER COUPLED LOGIC CIRCUITS; ERROR ANALYSIS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MULTIPLEXING EQUIPMENT; OPTIMIZATION; SWITCHING CIRCUITS;

BIPOLAR LOGIC DEVICE; CURRENT MODE LOGIC; ELECTRICAL PARAMETERS; HIGH SPEED INTEGRATED CIRCUITS; MULTIPLEXERS; POWER DISSIPATION; PROPAGATION DELAY; SOFTWARE PACKAGE SPICE;

DIGITAL INTEGRATED CIRCUITS;

EID: 0033739347     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.842113     Document Type: Article

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