CML and ECL: Optimized design and comparison

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 46, Issue 11, 1999, Pages 1330-1341

  Alioto, Massimo ^a   Palumbo, Gaetano ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES;

HIGH-SPEED INTEGRATED CIRCUITS;

EMITTER COUPLED LOGIC CIRCUITS;

EID: 0033224767     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.802823     Document Type: Article

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