Low store energy, low VDDmin, 8T2R nonvolatile latch and SRAM with vertical-stacked resistive memory (memristor) devices for low power mobile applications

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 6, 2012, Pages 1483-1496

  Chiu, Pi Feng ^a   Chang, Meng Fan ^a   Wu, Che Wei ^a   Chuang, Ching Hao ^a   Sheu, Shyh Shyuan ^a   Chen, Yu Sheng ^a   Tsai, Ming Jinn ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Low VDDmin; memristor; memristor latch; nonvolatile SRAM; nvSRAM; RRAM; vertical stacked

Indexed keywords

LOW VDDMIN; MEMRISTOR; NON-VOLATILE; NVSRAM; RRAM; VERTICAL-STACKED;

CELLS; CYTOLOGY; ENERGY UTILIZATION; FLASH MEMORY; MEMRISTORS; PASSIVE FILTERS; RESISTORS;

STATIC RANDOM ACCESS STORAGE;

EID: 84861720134     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2192661     Document Type: Article

References (58)

1. T. D. Burd et al., "A dynamic voltage scaled microprocessor system," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1571-1580, Nov. 2000. (Pubitemid 32070549)
2. K. J. Nowka et al., "A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1441-1447, Nov. 2002. (Pubitemid 35432164)
3. L. Yan et al., "Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed read-time embedded systems," IEEE J. Solid-State Circuits, vol. 24, no. 7, pp. 1030-1041, Jul. 2005. (Pubitemid 41013052)
4. M. E. Sinangil et al., "Areconfigurable 8T ultra-dynamic voltage scalable (U-DVS) SRAM in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3163-3173, Nov. 2005.
5. M.-F. Chang et al., "Wide VDD embedded asynchronous SRAM with dual-mode self-timed technique for dynamic voltage systems," IEEE Trans.Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp. 1657-1667, Aug. 2009.
6. Y. Morita et al., "An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp. 256-257. (Pubitemid 351306645)
7. M.-F. Chang et al., "A differential data-aware power-supplied (D AP) 8T SRAM cell with expanded write/read stabilities for lower VDDmin applications," IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1234-1245, Jun. 2010.
8. J.-J. Wu et al., "A large tolerant ZigZag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme," IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 815-827, Apr. 2011.
9. M.-F. Chang et al., "A 130 mV SRAM with expanded write and read margins for subthreshold applications," IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 520-529, Feb. 2011.
10. J. P. Kulkarni et al., "A 160 mV robust Schmitt trigger based subthreshold SRAM," IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313, Oct. 2007. (Pubitemid 47483011)
11. T.-H. Kim et al., "A high-density subthreshold SRAM with data-independent bitline leakage and virtual ground replica scheme," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 330-331.
12. N. Verma and A. P. Chandrakasan, "A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141-149, Jan. 2008.
13. B. Zhai et al., "A Sub-200 mV 6T SRAMin 0.13 mCMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 332-333.
14. B. H. Calhoun and A. Chandrakasan, "A 256 kb sub-threshold SRAM in 65 nm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 2592-2601.
15. M.-F. Chang and S.-J. Shen, "A process variation tolerant embedded split-gate flash memory using pre-stable current sensing scheme," IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 987-994, Mar. 2009.
16. M. Fliesler et al., "A 15 ns 4 Mb NVSRAM in 0.13 u SONOS technology," in Proc. Non-Volatile Semiconductor Memory Workshop (NVSMW), 2008, pp. 83-86.
17. N. Sakimura et al., "Nonvolatile magnetic flip-flop for standby-powerfree SoCs," IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2244-2250, Aug. 2009.
18. T. Miwa et al., "NV-SRAM: A nonvolatile SRAM with backup ferroelectric capacitors," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 522-527, Mar. 2001. (Pubitemid 32302994)
19. W. Wang et al., "Nonvolatile SRAM cell," in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, Dec. 2006, pp. 27-30.
20. M. Takata et al., "Nonvolatile SRAM based on phase change," in Non- Volatile Semiconductor Memory Workshop (NVSMW), Feb. 2006, pp. 95-96. (Pubitemid 44753370)
21. S.Yamamoto et al., "NonvolatileSRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices," in IEEE Custom Integrated Circuits Conf. (CICC) Tech. Dig. Papers, Sep. 2009, pp. 531-534.
22. G. Jackson et al., "A single-chip text-to-speech synthesis device utilizing analog nonvolatile multilevel flash storage," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1582-1589, Nov. 2002. (Pubitemid 35432180)
23. M. Hiraki et al., "A low-power microcontroller having a 0.5-uA standby current on-chip regulator with dual-reference scheme," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 661-666, April 2004.
24. M. Hatanaka and H. Hidaka, "Value creation in SOC/MCU applications by embedded nonvolatile memory evolutions," in IEEE Asia Solid-State Circuits Conf. (A-SSCC), Nov. 2007, pp. 38-42.
25. H. Hidaka, "Evolution of embedded flash memory technology for MCU," in IEEE Int. Conf. IC Design & Technology (ICICDT), May 2011, pp. 1-4.
26. K.-T. Tang et al., "A low-power electronic nose signal-processing chip for a portable artificial olfaction system," IEEE Trans. Biomed. Circuits Syst., vol. 5, no. 4, pp. 380-390, Aug. 2011.
27. D. Takashima et al., "A 128 Mb chain FeRAM and system design for HDD application and enhanced HDD performance," IEEE J. Solid- State Circuits, vol. 46, no. 2, pp. 530-536, Feb. 2011.
28. M. Qazi et al., "A low-voltage 1 Mb FeRAM in 0.13 m CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 208-209.
29. R. Nebashi et al., "A 90 nm 12 ns 32 Mb 2T1MTJ MRAM," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2010, pp. 462-463.
30. T. Kawahara et al., "2 Mb spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 280-281.
31. K.-J. Lee et al., "A 90 nm 1.8 V 512 Mb diode-switch PRAM with 266 MB/s read throughput," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 150-162, Jan. 2008.
32. S. Hanzawa et al., "A 512 kB embedded phase change memory with 416 kB/s write throughput at 100-A cell write current," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 474-475.
33. H. Y. Lee et al., "Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO based RRAM," in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, Dec. 2008, pp. 297-300.
34. Y. S. Chen et al., "Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity," in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, Dec. 2009, pp. 105-108.
35. H. Y. Lee et al., "Evidence and solution of Over-RESET problem for HfO based resistive memory with sub-ns switching speed and high endurance," in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, Dec. 2010, pp. 460-463.
36. H. Y. Lee et al., "Low-power and nanosecond switching in robust hafnium oxide resistive memory with a thin Ti cap," IEEE Electron Device Lett., vol. 31, no. 1, pp. 44-46, Jan. 2010.
37. S.-S. Sheu et al., "A 4 Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160 ns MLC-access capability," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 200-201.
38. C. J. Chevallier et al., "A 0.13- m 6 4 Mb multi-layered conductive metal-oxide memory," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2010, pp. 260-261.
39. K. Tsunoda et al., "Low power and high speed switching of Ti-doped NiO ReRAM under the unipolar voltage source of less than 3 V," in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, Dec. 2007, pp. 767-770.
40. Z. Wei et al., "Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism," in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, Dec. 2008, pp. 293-296.
41. D.-J. Seong et al., "Effect of oxygen migration and interface engineering on resistance switching behavior of reactive metal/polycrystalline Pr Ca MnO device for nonvolatile memory applications," in Int. Electron DevicesMeeting (IEDM) Tech. Dig. Papers, Dec. 2009, pp. 101-104.
42. J. Lee et al., "Diode-less nano-scale ZrO HfO RRAM device with excellent switching uniformity and reliability for high-density cross-point memory applications," in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, Dec. 2010, pp. 452-455.
43. W. C. Chien et al., "A forming-free WO resistive memory using a novel self-aligned field enhancement feature with excellent reliability and scalability," in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, Dec. 2010, pp. 440-443.
44. M. J. Lee et al., "Low power operating bipolarTMOReRAM for sub 10 nm era," in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, Dec. 2010, pp. 444-447.
45. C. H. Cheng et al., "Novel ultra-low power RRAM with good endurance and retention," in IEEE Symp. VLSI Technology Dig. Tech. Papers, Jun. 2010, pp. 85-86.
46. J. Hi et al., "Highly reliable and fast nonvolatile hybrid switching ReRAM memory using thin Al O demonstrated at 54 nm memory array," in IEEE Symp. VLSI Technology Dig. Tech. Papers, Jun. 2011, pp. 48-49.
47. X. A. Tran et al., "High performance unipolar AlO HfO Ni based RRAM compatible with Si diodes for 3D application," in IEEE Symp. VLSI Technology Dig. Tech. Papers, Jun. 2011, pp. 44-45.
48. M. Terai et al., "High thermal robust ReRAM with a new method for suppressing read disturb," in IEEE Symp. VLSI Technology Dig. Tech. Papers, Jun. 2011, pp. 50-51.
49. Y.-B. Kim et al., "Bi-layered RRAM with unlimited endurance and extremely uniform switching," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2011, pp. 52-53.
50. W. Kim et al., "Forming-free nitrogen-doped AlOx RRAM with sub-uA programming current," in IEEE Symp. VLSI Technology Dig. Tech. Papers, Jun. 2011, pp. 22-23.
51. L. O. Chua, "Memristor-The missing circuit element," IEEE Trans. Circuit Theory, vol. 18, no. 5, pp. 507-519, Sep. 1971.
52. R. Stanley Williams, "How we found the missing memristor," IEEE Spectrum, vol. 45, no. 12, pp. 28-35, 2008.
53. E. Seevinck et al., "Static noise margin analysis ofMOS SRAMcells," IEEE J. Solid-State Circuits, vol. 22, no. 5, pp. 748-754, Oct. 1987.
54. M.-F. Chang et al., "Experiments on reducing standby current for compilable SRAM using hidden clustered source line control," in Proc. IEEE Int. Conf. ASIC, Oct. 2007, pp. 1038-1041.
55. M. Yabuuchi et al., "A 45 nm 0.6 V cross-point 8T SRAM with negative biased read/write assist," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009, pp. 158-159.
56. T. Hirose et al., "A 20 ns 4 Mb CMOS SRAM with hierarchical word decoding architecture," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1990, pp. 132-133.
57. M. Yoshimoto et al., "A divided word-line structure in the static RAM and its application to a 64 K full CMOS RAM," IEEE J. Solid-State Circuits, vol. 18, no. 5, pp. 479-485, Oct. 1983. (Pubitemid 14506592)
58. M.-F. Chang et al., "A 0.45-V 300-MHz 10T flowthrough SRAM with expanded write/read stability and speed-area-wise array for sub-0.5-V chips," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 12, pp. 980-985, Dec. 2010.