A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 208-209

  Qazi, Masood ^a   Clinton, Michael ^b   Bartling, Steven ^b   Chandrakasan, Anantha P ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FERROELECTRIC RAM; FREQUENCY CONVERTERS;

ADVANCED TECHNOLOGY; FERROELECTRIC RANDOM ACCESS MEMORY; IMPLANTABLE MEDICAL DEVICES; LOW SUPPLY VOLTAGES; NON-VOLATILE MEMORY; NON-VOLATILE RAMS; PORTABLE ELECTRONICS; TIME TO DIGITAL CONVERTERS;

CMOS INTEGRATED CIRCUITS;

EID: 79955745764     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746285     Document Type: Conference Paper

References (4)

1. D. Takashima, et al., "A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM," ISSCC Digest Tech. Papers, pp. 262-263, 2010.
2. B. Jeon, M. Choi, Y. Song and K. Kim, "A nonvolatile ferroelectric RAM with common plate folded bit-line cell and enhanced data sensing scheme," ISSCC Digest Tech. Papers, pp. 38-39, 426, 2001.
3. T. S. Moise, et al., "Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process," IEDM Tech. Digest, pp. 535-538, 2002.
4. K. Yamaoka, et al., "A 0.9 V 1T1C SBT-based embedded non-volatile FeRAM with a reference voltage scheme and multi-layer shielded bit-line structure," ISSCC Digest Tech. Papers, pp. 50-512, 2004.