A 90nm 12ns 32Mb 2T1MTJ MRAM

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 462-464

  Nebashi, R ^a   Sakimura, N ^a   Honjo, H ^a   Saito, S ^a   Ito, Y ^b   Miura, S ^a   Kato, Y ^a   Mori, K ^a   Ozaki, Y ^b   Kobayashi, Y ^b   Ohshima, N ^a   Kinoshita, K ^a   Suzuki, T ^a   Nagahara, K ^a   Ishiwata, N ^a   Suemitsu, K ^a   Fukami, S ^a   Hada, H ^a   Sugibayashi, T ^a   Kasai, N ^a  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349268227     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977508     Document Type: Conference Paper

References (7)

1. J. Nahas, T. Andre, C. Subramanian, et al., "A 4Mb 0.18mm 1T1MTJ Toggle MRAM Memory," ISSCC Dig. Tech. Papers, pp. 44-45, Feb. 2004.
2. J. DeBrosse, C. Arndt, C. Barwin, et al., "A 16Mb MRAM Featuring Bootstrapped Write Drivers," Symp. VLSI Circuits, pp. 454-457, Jun. 2004.
3. Y. Iwata, K. Tsuchida, T. Inaba, et al., "A 16Mb MRAM with FORK Wiring Scheme and Burst Modes," ISSCC Dig. Tech. Papers, pp. 138-139, Feb. 2006.
4. T. Kawahara, R. Takemura, K. Miura, et al., "2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read," ISSCC Dig. Tech. Papers, pp. 480-481, Feb. 2007.
5. N. Sakimura, T. Sugibayashi, R. Nebashi, et al., "A 250-MHz 1-Mbit Embedded MRAM Macro Using 2T1MTJ Cell with Bitline Separation and Half-Pitch Shift Architecture," ASSCC Proc. Tech. Papers, pp. 216-217, Nov. 2007.
6. H. Honjo, S. Fukami, R. Nebashi, et al., "Performance of Shape-Varying MTJ for High- Speed MRAM Cells," Conference on Magnetism and Magnetic Materials, Nov. 2008.
7. H. Numata, T. Suzuki, N. Ohshima, et al., "Scalable Cell Technology Utilizing Domain Wall Motion for High-speed MRAM," Symp. VLSI Technology Dig. Tech. Papers, pp. 232-233, Jun. 2007.