Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias

Journal of Micromechanics and Microengineering

Volumn 22, Issue 5, 2012, Pages

  Dixit, Pradeep ^a   Vehmas, Tapani ^a   Vähänen, Sami ^a   Monnoyer, Philippe ^a   Henttinen, Kimmo ^b  

^a VTT TECHNICAL RESEARCH CENTRE OF FINLAND   (Finland)

^b Okemtic Oy   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM METALLIZATION; CMOS COMPATIBILITY; CONTACT PADS; ELECTRICAL CHARACTERIZATION; ELECTRICAL RESISTANCES; HEAVILY DOPED; HIGH ASPECT RATIO; HIGH-TEMPERATURE PROCESSING; KELVIN STRUCTURES; MEASURED RESULTS; SENSOR APPLICATIONS; SILICON DEVICES; THROUGH SILICON VIAS; VIA-FIRST;

ASPECT RATIO; CHEMICAL VAPOR DEPOSITION; ELECTRIC RESISTANCE; FABRICATION; HIGH TEMPERATURE APPLICATIONS; POLYSILICON; RECREATION CENTERS; SILICON WAFERS; STADIUMS;

WAFER BONDING;

EID: 84860465590     PISSN: 09601317     EISSN: 13616439     Source Type: Journal    
DOI: 10.1088/0960-1317/22/5/055021     Document Type: Article

References (29)

1. Garrou P, Bower C and Ramm P 2008 Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits (NewYork: Wiley-VCN)
2. Alsarawi S F, Abbott D and Franzon P D 1998 A review of 3D packaging technology IEEE Trans. Compon. Packag. Manuf. Technol. B 21 214
3. Poupon G, Sillon N, Henry D, Gillot C, Mathewson A, Dicioccio L, Charlet B, Leduc P, Vinet M and Batude P 2009 System on wafer: a new silicon concept in SiP Proc. IEEE 97 609
4. Lu J Q 2009 3D hyperintegration and packaging technologies for micro-nano systems Proc. IEEE 97 1830
5. Koyanagi M, Fukushima T and Tanaka T 2009 High-density through silicon vias for 3D LSIs Proc. IEEE 97 4959
6. Kang U et al 2010 8 Gb 3D DDR3 DRAM using through-silicon-Via technology IEEE J. Solid-State Circuits 45 1119
7. Knickerbocker J U et al 2008 Three-dimensional silicon integration IBM J. Res. Dev. 52 55369
8. Knickerbocker J U et al 2005 Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection IBM J. Res. Dev. 49 72553 (Pubitemid 41398417)
9. Dixit P, Miao J and Preisser R 2006 Fabrication of high aspect ratio 35 m pitch through-wafer copper interconnects by electroplating for 3D wafer stacking Electrochem. Solid-State Lett. 9 G3058 (Pubitemid 44270901)
10. Gu C, Xu H and Zhang T Y 2009 Fabrication of high aspect ratio through-wafer copper interconnects by reverse pulse electroplating J. Micromech. Microeng. 19 065011
11. Ramm P, Wolf M J, Klumpp A, Wieland R, Wunderle B, Michel B and Reichl H 2008 Through silicon via technology - processes and reliability for wafer-level 3D system integration IEEE Elec. Comp. Tech. Conf. pp. 8416
12. Ranganathan N, Prasad K, Balasubramanian N and Pey K L 2008 A study of thermo-mechanical stress and its impact on through-silicon vias J. Micromech. Microeng. 18 075018
13. Liu X, Chen Q, Dixit P, Chatterjee R, Tummala R and Sitaraman S 2009 Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV) IEEE Elec. Comp. Tech. Conf. pp 6249
14. Dixit P, Yaofeng S, Miao J, Pang J H L, Chatterjee R and Tummala R R 2008 Numerical and experimental investigation of thermo-mechanical deformation in high-aspect-ratio electroplated through-silicon vias J. Electrochem. Soc. 155 H9816
15. Kawano M, Takahashi N, Kurita Y, Soejima K, Komuro M and Matsui S 2008 Three-dimensional packaging technology for stacked DRAM with 3-Gb/s data transfer IEEE Trans. Electron Devices 55 161420
16. Henry D, Baillin X, Lapras V, Vaudaine M, Quemper J, Sillon N, Dunne B, Hernandez C and Vigier-Blanc E 2007 Via first technology development based on high aspect ratio trenches filled with doped polysilicon IEEE Elec. Comp. Tech. Conf. pp 8305 (Pubitemid 47577127)
17. Lietaer N, Storas P, Breivik L and Moe S 2006 Development of cost-effective high-density through-wafer interconnects for 3D microsystems J. Micromech. Microeng. 16 S2934
18. Chow E M, Chandrasekaran V, Partridge A, Nishida T, Sheplak M, Quate C F and Kenny T W 2002 Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates J. Micromech. Syst. 11 63140
19. Krishnamurthy R and Gibb K 2008 Drilling and filling, but not in your Dentist's chair Chip Des. Mag. 313 (http://chipdesignmag.com/display.php? articleId=2641)
20. Ji F, Leppavuori S, Luusua I, Henttinen K, Eranen S, Hietanen I and Juntunen M 2008 Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging Sensors Actuators A 142 40512 (Pubitemid 351199554)
21. Li R, Lamy Y, Besling W, Roozeboom F and Sarro P M 2008 Continuous deep reactive ion etching of tapered via holes for three-dimensional integration J. Micromech. Microeng. 18 125023
22. Dixit P and Miao J 2008 High aspect ratio vertical through-vias for 3D MEMS packaging applications by optimized three-step deep RIE J. Electrochem. Soc. 155 H8591
23. Velden P 2000 Chemical mechanical polishing with fixed abrasives using different subpads to optimize wafer uniformity Microelectron. Eng. 50 416 (Pubitemid 32211795)
24. Suni T, Henttinen K, Lipsanen A, Dekker J, Luoto H and Kulawski M 2006 Wafer scale packaging of MEMS by using plasma-activated wafer bonding J. Electrochem. Soc. 153 G7882
25. Chung C 2004 Geometrical pattern effect on silicon deep etching by an inductively coupled plasma system J. Micromech. Microeng. 14 65662
26. Sze S M 1998 VLSI Technology (NewYork: Mcgraw-Hill)
27. McConnell A D, Uma S and Goodson K E 2001 Thermal conductivity of doped polysilicon layers IEEE J. Microelectromech. Syst. 10 3609 (Pubitemid 32981787)
28. Agarwal A, Murthy R B, Lee V and Viswanadam G 2009 Polysilicon interconnections (FEOL): fabrication and characterization IEEE Elec. Pack. Tech. Conf. pp 31720
29. Pares G, Bresson N, Moreau S, Lapras V, Henry D and Sillon N 2010 Effects of stress in polysilicon VIA - first TSV technology IEEE Elec. Pack. Tech. Conf. pp 3337