Polysilicon interconnections (FEOL): Fabrication and characterization

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2009, Pages 317-320

  Agarwal, Ajay ^a,b   Murthy, Ramana B ^a   Lee, Vincent ^a   Viswanadam, Gautham ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b Loyang Industrial Estate   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED PACKAGING; CMOS DEVICES; CMOS SCALING; DOPED POLYSILICON; ELECTRICAL ANALYSIS; ENABLING TECHNOLOGIES; HIGH DENSITY; SILICON CARRIERS; SILICON INTEGRATION; THROUGH-SILICON-VIA;

CMOS INTEGRATED CIRCUITS; ELECTRONICS PACKAGING; PACKAGING; POLYSILICON; TECHNOLOGY;

SILICON WAFERS;

EID: 77950940315     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2009.5416531     Document Type: Conference Paper

References (5)

1. Andry, P S, C K Tsang, B C Webb, E J Sprogis, S L Wright, B Dang, and D G Manzer, "Fabrication and Characterization of Robust Through-Silicon Vias for Silicon-Carrier Applications," IBM J. Res. & Dev., Vol.52, No.6, Nov. (2008) pp. 571-581
2. Ramaswami, S, B Eaton, J Dukovic, N Khurana, S Xia, B Chandrasekaran, and K Sapre, "Through-Silicon Via Technologies - Challenges and solutions," Nanochip Technology Journal, Vol.2 (2008) pp.14-22
3. Motoyoshi, M and M Koyanagi, "3D-LSI technology for image sensor," J. Inst, 4 (2009) pp. 03009
4. Ranganathan, N, L Ebin, L Linn, W S Lee, Vincent, O K Navas, V Kripesh, and N. Balasubramanian, "Integration of High Aspect Ratio Tapered Silicon Via for Silicon Carrier Fabrication," IEEE Tran. on Adv. Packaging, Vol.32, No.1 (2009) pp. 62-71
5. th Electronic Components and Technology Conf, Reno, Nevada, May-June, 2007 May, pp. 830-835.