Fabrication of high aspect ratio 35 μm pitch through-wafer copper interconnects by electroplating for 3-D wafer stacking

Electrochemical and Solid-State Letters

Volumn 9, Issue 10, 2006, Pages

  Dixit, Pradeep ^a,c   Miao, Jianmin ^a   Preisser, Robert ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b ATOTECH DEUTSCHLAND GMBH   (Germany)

^c ELECTROCHEMICAL SOCIETY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROPLATING PROCESS PARAMETERS; HIGH-DENSITY ELECTRONIC PACKAGING; THREE-DIMENSIONAL (3-D) WAFER STACKING; UNIFORM METAL DEPOSITION;

COPPER; ELECTRIC CURRENT DISTRIBUTION; ELECTRODEPOSITION; FABRICATION; PARAMETER ESTIMATION; PROCESS ENGINEERING; WSI CIRCUITS;

ELECTROPLATING;

EID: 33747670896     PISSN: 10990062     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.2236374     Document Type: Article

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