Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging

Sensors and Actuators, A: Physical

Volumn 142, Issue 1, 2008, Pages 405-412

  Ji, Fan ^a   Leppävuori, Seppo ^b   Luusua, Ismo ^c   Henttinen, Kimmo ^c   Eränen, Simo ^c   Hietanen, Iiro ^a   Juntunen, Mikko ^a  

^a Detection Technology Inc   (Finland)

^b UNIVERSITY OF OULU   (Finland)

^c VTT TECHNICAL RESEARCH CENTRE OF FINLAND   (Finland)

Author keywords

Chip scale packaging (CSP); Failure mechanism; Metal oxide semiconductor (MOS); Through wafer interconnects (TWIs)

Indexed keywords

CHIP SCALE PACKAGES; ELECTRIC INSULATION; FLIP CHIP DEVICES; LARGE SCALE SYSTEMS; MOS DEVICES; SEMICONDUCTOR DEVICE MODELS;

FAILURE MECHANISM; FLIP-CHIP TECHNOLOGY; LARGE SCALE DETECTOR ARRAYS; THROUGH-WAFER INTERCONNECTS (TWI);

OPTICAL INTERCONNECTS;

EID: 38849136535     PISSN: 09244247     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sna.2007.02.030     Document Type: Article

References (13)

1. Kim S., Bang B.S., Ren F., D'entremont J., Blumenfeld W., Cordock T., and Pearton S.J. SiC via holes by laser drilling. J. Electron. Mater. 33 (2004) 477-480
2. Polyakov A., Grob T., Hovenkamp R.A., Kettelarij H.J., Eidner I., de Samber M.A., Bartek M., and Burghartz J.N. Comparison of via-fabrication techniques for through-wafer electrical interconnect applications. 54th ECTC Conference, June 1-4 (2004) 1466-1470
3. Chow E.M., Chandrasekaran V., Partridge A., Nishida T., Sheplak M., Quate C.F., and Kenny T.W. Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates. J. Microelectromech. Syst. 11 (2002) 631-640
4. Leung L.L.W., and Chen K.J. Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates. IEEE Trans. Microwave Theory Techn. 53 (2005) 2472-2480
5. Johnson V.N., Jozwiak J., and Moll A. Through wafer interconnects on active pMOS devices. Proceedings of IEEE Workshop on Microelectronics and Electron Devices (2004) 82-84
6. Wu J.H., Scholvin J., and del Alamo J.A. A through-wafer interconnect in silicon for RFICs. IEEE Trans. Electron Device 51 (2004) 1765-1771
7. Chandrasekaran V., Chow E.M., Kenny T.W., Nishida T., Cattafesta L.N., Sankar B.V., and Sheplak M. Thermoelastically actuated acoustic proximity sensor with integrated through-wafer interconnects. Solid-state Senor Actuator And Microsystems Workshop. South Carolina, June 2-6 (2002) 102-107
8. I. Luusua, K. Henttinen, P. Pekko, T. Vehmas, H. Luoto, Through-wafer polysilicon interconnect fabrication with in situ boron doping, in: 2005 MRS Spring Meeting, Symposium J, Micro- and Nanosystems - Materials and Devices, Vol. 872, Materials Research Society (2005), pp. 77-81.
9. Ok S.J., Kim C., and Baldwin D.F. High density high aspect ratio through-wafer electrical interconnect vias for MEMS packaging. IEEE Trans. Adv. Packaging 26 (2003) 302-309
10. Wang L., Visser C.C.G., de Boer C., Laros M., van der Vlist W., Groeneweg J., Craciun G., and Sarro P.M. Thinning of micromachined wafers for high-density through-wafer interconnects. Proceeding of SAFE2002. Veldhoven (2002) 121-126
11. Sze S.M. Semiconductor Devices: Physics and Technology. second ed. (2002), Wiley, New York pp. 175-185
12. Nam S.H., Kim B.H., and Moon J. In situ boron-doped polycrystalline silicon films prepared by a novel low-pressure chemical vapour deposition method using a Si2H6-B2H6-N2 gas system. J. Phys. D: Appl. Phys. 29 (1996) 1088-1092
13. Ranganathan N., Prasad K., Balasubramanian N., Qiaoer Z., and Hwee S.C. High aspect ratio through-wafer interconnect for three dimensional integrated circuits. Electronic Components And Technology Conference (2005) 343-348