Three-dimensional packaging technology for stacked DRAM with 3-Gb/s data transfer

IEEE Transactions on Electron Devices

Volumn 55, Issue 7, 2008, Pages 1614-1620

  Kawano, Masaya ^a   Takahashi, Nobuaki ^a   Kurita, Yoichiro ^a   Soejima, Koji ^a   Komuro, Masahiro ^a   Matsui, Satoshi ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

3 D packaging; Interposer; Stacked dynamic random access memory (DRAM); Through silicon vias (TSVs)

Indexed keywords

BIOCONVERSION; CHIP SCALE PACKAGES; DATA TRANSFER; DYNAMIC RANDOM ACCESS STORAGE; ELECTRONIC EQUIPMENT MANUFACTURE; POLYSILICON; PROCESS DESIGN; PROCESS ENGINEERING; RANDOM ACCESS STORAGE; SILICON; SILICON WAFERS; TECHNOLOGY; TECHNOLOGY TRANSFER; THREE DIMENSIONAL; TRANSFER FUNCTIONS;

(100) SILICON; (E ,3E) PROCESS; (OTDR) TECHNOLOGY; 3-D PACKAGING; DYNAMIC RANDOM-ACCESS MEMORY (DRAM); FEEDTHROUGH; LAYOUT DESIGNS; MEMORY CONTROLLERS; NORMAL OPERATION; POLY-SI; PROCESS CONDITIONS; SI ETCHING; SIMULATION AND MEASUREMENT; THREE DIMENSIONAL (3-D) PACKAGING; THROUGH SILICON VIAS (TSV); TRANSFER CAPABILITY; WAFER LEVELS;

ELECTRONICS PACKAGING;

EID: 46649090123     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.924068     Document Type: Article

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