Via first technology development based on high aspect ratio trenches filled with doped polysilicon

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 830-835

  Henry, D ^a   Baillin, X ^a   Lapras, V ^a   Vaudaine, M H ^a   Quemper, J M ^a   Sillon, N ^a   Dunne, B ^b   Hernandez, C ^b   Vigier Blanc, E ^b  

^a CEA GRENOBLE   (France)

^b STMICROELECTRONICS   (France)

Author keywords

3D integration; Backside technology; Doped polysilicon filling; DRIE; Electrical resistance; High aspect ratio trenches; Via first

Indexed keywords

ASPECT RATIO; CMOS INTEGRATED CIRCUITS; HIGH TEMPERATURE EFFECTS;

3D INTEGRATION; DOPED POLYSILICON FILLING; HIGH ASPECT RATIO TRENCHES;

POLYSILICON;

EID: 35348876001     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.373894     Document Type: Conference Paper

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