Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV)

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 624-629

  Liu, Xi ^a   Chen, Qiao ^a   Dixit, Pradeep ^a   Chatterjee, Ritwik ^a   Tummala, Rao R ^a   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Finite element modeling; Thermo mechanical reliability; Through silicon via; Xrd measurements

Indexed keywords

COEFFICIENT OF THERMAL EXPANSION; COHESIVE CRACKS; CONDUCTING MATERIALS; CU/SIO2; ELECTRICAL DESIGN; ELECTROPLATED COPPER; ENABLING TECHNOLOGIES; EXPERIMENTAL DATA; FAILURE MECHANISM; FINITE-ELEMENT MODELING; FINITE-ELEMENT MODELS; FRACTURE ANALYSIS; FRACTURE MECHANICS ANALYSIS; INTERFACIAL CRACKS; MECHANICAL DESIGN; OPTIMUM DESIGNS; STRESS GRADIENT; STRESS/STRAIN; THERMO-MECHANICAL; THERMO-MECHANICAL ANALYSIS; THERMO-MECHANICAL RELIABILITY; THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS; THROUGH SILICON VIA; THROUGH SILICON VIAS; WAFER LEVEL PACKAGING; XRD; XRD MEASUREMENTS;

CRACKS; ELECTRIC CONVERTERS; FRACTURE; FRACTURE MECHANICS; INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; MACHINE DESIGN; MECHANISMS; RELIABILITY; SEMICONDUCTING SILICON COMPOUNDS; SILICON OXIDES; SILICON WAFERS; STRESSES; STRUCTURAL DESIGN; TECHNOLOGY; THERMAL EXPANSION; THERMOMECHANICAL TREATMENT; THREE DIMENSIONAL; X RAY DIFFRACTION; X RAY DIFFRACTION ANALYSIS;

FINITE ELEMENT METHOD;

EID: 70349675218     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074078     Document Type: Conference Paper

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