Effects of stress in polysilicon VIA - First TSV technology

2010 12th Electronics Packaging Technology Conference, EPTC 2010

Volumn , Issue , 2010, Pages 333-337

  Pares G ^a   Bresson, N ^a   Moreau, S ^a   Lapras, V ^a   Henry, D ^a   Sillon, N ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

3D STACKING; ATTRACTIVE SOLUTIONS; CMOS DEVICES; CRYSTALLINE DEFECTS; ELECTRICAL PERFORMANCE; IMPACT PERFORMANCE; KEY PROCESS; PROCESS STEPS; SILICON SUBSTRATES; SIMULATED DATA; STRESS RELEASE; STRESS-INDUCED; THIN WAFERS; THROUGH-SILICON-VIA; VIA-FIRST; WAFER LEVEL; WARPAGES;

CHIP SCALE PACKAGES; DEFECTS; ELECTRONIC EQUIPMENT MANUFACTURE; EXPANSION; POLYSILICON; SILICON WAFERS; TECHNOLOGY;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 79951935678     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2010.5702658     Document Type: Conference Paper

References (9)

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