High-density through silicon vias for 3-D LSIs

Proceedings of the IEEE

Volumn 97, Issue 1, 2009, Pages 49-60

  Koyanagi, Mitsumasa ^a   Fukushima, Takafumi ^a   Tanaka, Tetsu ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

3 D system in package (SiP); Microbump; Three dimensional (3 D) large scale integration (LSI); Through silicon via (TSV); Wafer bonding; Wafer thinning

Indexed keywords

ATOMIC LAYER DEPOSITION; CHEMICAL BONDS; INTEGRATED CIRCUIT INTERCONNECTS; LSI CIRCUITS; POLYCRYSTALLINE MATERIALS; SILICON WAFERS; SYSTEM-IN-PACKAGE; VAPOR DEPOSITION; WAFER BONDING;

3-D SYSTEM-IN-PACKAGE (SIP); MICRO-BUMPS; THREEDIMENSIONAL (3-D); THROUGH-SILICON-VIA (TSV); WAFER THINNING;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 61549132828     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2008.2007463     Document Type: Article

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