Understanding the potential and the limits of Germanium pMOSFETs for VLSI circuits from experimental measurements

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 9, 2011, Pages 1569-1582

  Magnone, P ^a   Crupi, F ^a   Alioto, M ^b,c   Kaczer, B ^d   De Jaeger, B ^d  

^a UNIVERSITY OF CALABRIA   (Italy)

^b UNIVERSITY OF SIENA   (Italy)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d IMEC   (Belgium)

Author keywords

Digital circuits; emerging technologies; germanium; leakage delay tradeoff; VLSI

Indexed keywords

65-NM NODE; BODY BIASING; CIRCUIT DESIGN TOOLS; CIRCUIT LEVELS; DEVICE PARAMETERS; DYNAMIC POWER; EMERGING TECHNOLOGIES; EQUIVALENT OXIDE THICKNESS; EXPERIMENTAL MEASUREMENTS; FIGURES OF MERITS; GATE STACKS; GERMANIUM DEVICES; GERMANIUM TRANSISTORS; LEAKAGE-DELAY TRADEOFF; MAIN CIRCUIT PARAMETER; MOSFETS; P-MOSFETS; PMOSFET; POWER GATINGS; STACK FORCING; SYSTEM LEVELS; VLSI; VLSI DESIGN; VOLTAGE-SCALING;

DIGITAL CIRCUITS; ELECTRIC NETWORK ANALYSIS; ENERGY EFFICIENCY; GERMANIUM; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; MOSFET DEVICES;

VLSI CIRCUITS;

EID: 79960994642     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2053226     Document Type: Article

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